DP84910_11 Datasheet, PDF (26/34 Pages) Texas Instruments – DP84910 DP84910-36 DP84910-50 Integrated Read Channel

Pulse Detector Description (Continued)
TABLE IV Servo Control Truth Table
HOLD
S1
S2
S3
S4
Function
0
0
0
0
0
Previously Latched Mode
0
1
0
0
0
Latch Track Follow Mode
0
0
1
0
0
Output Internal Signals and Previously Latched Mode
0
1
1
0
0
Output Internal Signals and Latch Track Follow Mode
0
0
0
1
0
Latch Seek Mode
0
1
0
1
0
Not Allowed
0
0
1
1
0
Output Internal Signals and Latch Seek Mode
0
1
1
1
0
Not Allowed
0
0
0
0
1
Discharge Servo Caps and Previously Latched Mode
0
1
0
0
1
Discharge Servo Caps and Latch Track Follow Mode
0
0
1
0
1
Discharge Servo Caps and Output Internal Signals
0
1
1
0
1
Discharge Servo Caps Output Internal Signals and Latch Track Follow Mode
0
0
0
1
1
Discharge Servo Caps and Latch Seek Mode
0
1
0
1
1
Not Allowed
0
0
1
1
1
Discharge Servo Caps Output Internal Signals and Latch Seek Mode
0
1
1
1
1
Not Allowed
1
0
0
0
0
Previously Latched Mode
1
1
0
0
0
Gate On SCAP1 and Previously Latched Mode
1
0
1
0
0
Gate On SCAP2 and Previously Latched Mode
te ¹
1
1
0
0
Gate On SCAP1 SCAP2 and Previously Latched Mode
1
0
0
1
0
Gate On SCAP3 and Previously Latched Mode
1
1
0
1
0
Gate On SCAP1 SCAP3 and Previously Latched Mode
1
0
1
1
0
Gate On SCAP2 SCAP3 and Previously Latched Mode
1
1
1
1
0
Gate On SCAP1 SCAP2 SCAP3 and Previously Latched Mode
1
0
0
0
1
Gate On SCAP4 and Previously Latched Mode
le ¹
1
0
0
1
Gate On SCAP1 SCAP4 and Previously Latched Mode
1
0
1
0
1
Gate On SCAP2 SCAP4 and Previously Latched Mode
1
1
1
0
1
Gate On SCAP1 SCAP2 SCAP4 and Previously Latched Mode
1
0
0
1
1
Gate On SCAP3 SCAP4 and Previously Latched Mode
1
1
0
1
1
Gate On SCAP1 SCAP3 SCAP4 and Previously Latched Mode
1
0
1
1
1
Gate On SCAP2 SCAP3 SCAP4 and Previously Latched Mode
1
1
1
1
1
Gate On SCAP1 SCAP2 SCAP3 SCAP4 and Previously Latched Mode
o _{Channel Filter Description}
The integrated channel filter is a continuous-time analog im-
plementation of an 0 05 degree error equal ripple LC ladder
s _{filter as shown in Figure 8 The equal ripple filter was cho-}
sen because it has extended phase linearity and better am-
plitude response in the stop band when compared to other
filter types of the same order The amount of pulse slimming
is selectable by control register bits in eight steps with a
b _{maximum 9 dB of peaking The filter’s b3 dB frequency is}
selectable by control register bits in a maximum of 128
steps Dual b3 dB frequencies one for data field and one
for servo field are selectable by control register bits and
multiplexed by the SFIELD pin (when enabled by control
O ^{register bit SERVO) The SFIELD pin control allows for the}
filter characteristics remain independent of supply tempera-
ture and process variations This PLL locks to the frequency
provided at the XTLIN pin
altering of the channel filter bandwidth on the fly without
accessing the control register Dual AGC control pins one
for data field and one for servo field insures quick settling
TL F 11777 – 8
times when the filter bandwidth is changed in this manner A
C1 e 23 86 pF C3 e 13 4 pF
C5 e 10 25 pF C7 e 3 042 pF
dedicated PLL for the channel filter is included to ensure the
L2 e 16 03 mH L4 e 11 81 mH L6 e 7 63 mH
R1 e2 kX
FIGURE 8 Equal Ripple Filter LC Equivalent
25
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