CDCM61001_17 Datasheet, PDF (26/35 Pages) Texas Instruments – One Output, Integrated VCO, Low-Jitter Clock Generator

CDCM61001
SCAS869F – FEBRUARY 2009 – REVISED JUNE 2011
www.ti.com
Interfacing Between LVPECL and HCSL
Because the LVPECL common-mode voltage is different from the HCSL common-mode voltage, ac-coupled
termination is used. The 150-Ω resistor ensures proper biasing of the CDCM61001 LVPECL output stage, while
the 471-Ω and 56-Ω resistor network biases the HCSL receiver input stage, as shown in Figure 25.
CDCM61001
150 W
0W
0W
150 W
471 W
V_{CC_OUT}
471 W
V_{CC_OUT}
56 W
56 W
HCSL
Figure 25. LVPECL to HCSL Interface
26
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