ADS8331_15 Datasheet, PDF (26/57 Pages) Texas Instruments – Low-Power, 16-Bit, 500-kSPS, 4-/8-Channel Unipolar Input Analog-to-Digital Converters

ADS8331, ADS8332
SBAS363D – DECEMBER 2009 – REVISED OCTOBER 2015
www.ti.com
The ADS833x can support sampling rates of up to 500 kSPS in Auto-Trigger mode. This rate is selectable by
programming the CFR_D8 bit in the Configuration register. In 500-kSPS mode, consecutive conversion start
pulses to the analog core are generated 21 conversion clock cycles apart. In 250-kSPS mode, consecutive
conversion-start pulses are 42 conversion clock cycles apart. The Nap and Deep Power-Down modes are
available with either sampling rate; however, Auto-NAP mode is available only with a sampling rate of 250 kSPS
when Auto-Trigger mode is enabled. The analog core cannot be powered down when the Auto-NAP mode
sampling rate is 500 kSPS because at that rate, there is no period of time when the analog core is not actively
being used.
Figure 42 shows the timing diagram for conversion start and Auto-NAP power-down signals for a 250-kSPS
sampling rate in Auto-Trigger mode. For a 16-bit ADC output word, consecutive new conversion start pulses are
generated 2 × (18 + 3) cycles apart. NAP_ACTIVE (the signal to power down the analog core in Nap and Auto-
NAP modes) goes low six (3 + 3) conversion clock cycles before the conversion start falling edge, thus powering
up the analog core. It takes three conversion clock cycles after NAP_ACTIVE goes low to power up the analog
core. The analog core is powered down a cycle after the end of a conversion. For a 16-bit ADC with a 500-kSPS
sampling rate and three conversion clock cycle sampling, consecutive conversion start pulses are generated 21
conversion clock cycles apart.
CCLK
1
2
3
19 20
21
37
38
42
43
CONVST_OUT
(internal)
EOC
(active low)
NAP_ACTIVE
(internal)
Figure 42. Timing for Conversion Start and Auto-NAP Power-Down Signals in Auto-Trigger Mode (250-
kSPS Sampling and Three Conversion Clock Cycles for Acquisition)
Timing diagrams for reading from the ADS833x with various trigger and power-down modes are shown in
Figure 43 through Figure 45. The total (acquisition + conversion) times for the different trigger and power-down
modes are listed in Table 3.
Table 3. Total Acquisition + Conversion Times
MODE
ACQUISITION + CONVERSION TIME
Auto-Trigger at 500 kSPS
= 21 CCLK
Manual-Trigger
≥ 21 CCLK
Manual-Trigger with Deep Power Down ≥ 4 SCLK + 1 μs + 3 CCLK + 18 CCLK + 16 SCLK + 2 μs
Manual-Trigger with Nap Power Down ≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK + 16 SCLK + 200 ns
≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK + 1 CCLK + 200 ns (using wakeup to resume)
Manual-Trigger with Auto-NAP Power Down
≥ 3 CCLK + 3 CCLK + 18 CCLK + 1 CCLK + 200 ns (using CONVST to resume)
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