ADC12DS080 Datasheet, PDF (26/34 Pages) Texas Instruments – 80 MSPS A/D Converter

ADC12DS080
SNAS443A – MARCH 2008 – REVISED MARCH 2013
Table 3. User Test Pattern Register 0, Address 1h
7
6
5
4
3
2
1
Reserved
User Test Pattern (13:6)
www.ti.com
0
Reset State : 00h
Bits (7:6)
Bits (5:0)
Reserved. Must be set to '0'.
User Test Pattern. Most-significant 6 bits of the 12-bit pattern that will be sourced out of the data outputs in
Test Output Mode.
Table 4. User Test Pattern Register 1, Address 2h
7
6
5
4
3
2
1
0
User Test Pattern (5:0)
Reserved
Reset State : 00h
Bits (7:2)
Bits (1:0)
User Test Pattern. Least-significant 6 bits of the 12-bit pattern that will be sourced out of the data outputs in
Test Output Mode.
Reserved. Must be set to '0'.
POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 0.1 µF capacitor and with a 100 pF ceramic chip capacitor
close to each power pin. Leadless chip capacitors are preferred because they have low series inductance.
As is the case with all high-speed converters, the ADC12DS080 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100 mV_P-P.
No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be
especially careful of this during power turn on and turn off.
LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining
separate analog and digital areas of the board, with the ADC12DS080 between these areas, is required to
achieve specified performance.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the
clock line as short as possible.
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area
is more important than is total ground plane area.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in
high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to
keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the
generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause
problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to
degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.
Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the
signal path through all components should form a straight line wherever possible.
Be especially careful with the layout of inductors and transformers. Mutual inductance can change the
characteristics of the circuit in which they are used. Inductors and transformers should not be placed side by
side, even with just a small part of their bodies beside each other. For instance, place transformers for the analog
input and the clock input at 90° to one another to avoid magnetic coupling.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to
the reference input pin and ground should be connected to a very clean point in the ground plane.
26
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: ADC12DS080