TWL1200-Q1 Datasheet, PDF (25/32 Pages) Texas Instruments – SDIO, UART, AND AUDIO VOLTAGE-TRANSLATION TRANSCEIVER

TWL1200-Q1
www.ti.com
SCES832A – MARCH 2012 – REVISED MARCH 2012
PRINCIPLES OF OPERATION
Applications
The TWL1200-Q1 device has been designed to bridge the digital-switching compatibility gap between two
voltage nodes to interface successfully the logic threshold levels between a host processor and the Texas
Instruments Wi-Link-6 WLAN/BT/FM products. The device is intended to be used in a point-to-point topology
when interfacing these devices that may or may not be operating at different interface voltages.
Architecture
The BT/UART and PCM/Audio subsystem interfaces consist of a fully-buffered voltage translator design that has
its output transistors to source and sink current optimized for drive strength.
The SDIO lines constitute a semi-buffered auto-direction-sensing based translator architecture (see Figure 27)
that does not require a direction-control signal to control the direction of data flow of the A to B ports (or from B
to A ports).
V_CCA
V_CCB
R1
One-Shot
T1
R2
Translator
One-Shot
T2
SDIO-DATAx(A)
Bias
N1
SDIO-DATAx(B)
T3
One-Shot
T4
One-Shot
Translator
Figure 27. Architecture of an SDIO Switch-Type Cell
Each of these bidirectional SDIO channels independently determines the direction of data flow without a
direction-control signal. Each I/O pin can be automatically reconfigured as either an input or an output, which is
how this auto-direction feature is realized.
The following two key circuits are employed to facilitate the switch-type voltage-translation function:
1. Integrated pullup resistors to provide dc-bias and drive capabilities
2. An N-channel pass-gate transistor topology (with a high R_ON of approximately 300 Ω) that ties the A-port to
the B-port
3. Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B
ports
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): TWL1200-Q1
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