TPS71H01 Datasheet, PDF (25/45 Pages) Texas Instruments – LOW-DROPOUT VOLTAGE REGULATORS

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q
LOWĆDROPOUT VOLTAGE REGULATORS
SLVS152B − NOVEMBER 1996 − REVISED AUGUST 2002
THERMAL INFORMATION
standard TSSOP-20 (continued)
For a 20-lead TSSOP / FR4 board system with thermally conductive compound between the board and the
device body, where T_A = 55°C, airflow = 100 ft /min, copper heat sink area = 1 cm², the maximum
power-dissipation limit can be calculated. As indicated in Figure 45, the system R_θJA is 94°C/W; therefore, the
maximum power-dissipation limit is:
PD(max)
+
TJ(max) * TA
R _qJA(system)
+
125°C * 55
94°Cń W
°C
+
745
mW
If the system implements a TPS71H48 regulator where V_I = 6 V and I_O = 385 mA, the internal power dissipation
is:
ǒ Ǔ _{PD(total) + VI * VO @ IO + (6 * 4.85) @ 0.385 + 443 mW}
Comparing P_D(total) with P_D(max) reveals that the power dissipation in this example does not exceed the
maximum limit. When it does, one of two corrective actions can be taken. The power-dissipation limit can be
raised by increasing the airflow or the heat-sink area. Alternatively, the internal power dissipation of the regulator
can be lowered by reducing the input voltage or the load current. In either case, the above calculations should
be repeated with the new system parameters.
thermally enhanced TSSOP-20
The thermally enhanced PWP package is based on the 20-pin TSSOP, but includes a thermal pad [see
Figure 46(c)] to provide an effective thermal contact between the IC and the PWB.
Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down
TO220-type packages have leads formed as gull wings to make them applicable for surface-mount applications.
These packages, however, suffer from several shortcomings: they do not address the very low profile
requirements (< 2 mm) of many of today’s advanced systems, and they do not offer a pin-count high enough
to accommodate increasing integration. On the other hand, traditional low-power surface-mount packages
require power-dissipation derating that severely limits the usable range of many high-performance analog
circuits.
The PWP package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal
performance comparable to much larger power packages.
The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and
limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction
paths that remove heat from the component. The thermal pad is formed using a lead-frame design (patent
pending) and manufacturing technique to provide the user with direct connection to the heat-generating IC.
When this pad is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the
ultrathin, fine-pitch, surface-mount package can be reliably achieved.
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