SM320C6713-EP_15 Datasheet, PDF (25/133 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SM320C6713-EP
SM320C6713B-EP
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Table 4-7. EDMA Registers
SGUS049K – AUGUST 2003 – REVISED APRIL 2011
HEX ADDRESS RANGE
01A0 0800−01A0 FEFC
01A0 FF00
01A0 FF04
01A0 FF08−01A0 FF0B
01A0 FF0C
01A0 FF1F−01A0 FFDC
01A0 FFE0
01A0 FFE4
01A0 FFE8
01A0 FFEC
01A0 FFF0
01A0 FFF4
01A0 FFF8
01A0 FFFC
01A1 0000−01A3 FFFF
ACRONYM
—
ESEL0
ESEL1
—
ESEL3
—
PQSR
CIPR
CIER
CCER
ER
EER
ECR
ESR
—
REGISTER NAME
Reserved
EDMA event selector 0
EDMA event selector 1
Reserved
EDMA event selector 3
Reserved
Priority queue status register
Channel interrupt pending register
Channel interrupt enable register
Channel chain enable register
Event register
Event enable register
Event clear register
Event set register
Reserved
Table 4-8. Quick DMA (QDMA) and Pseudo Registers⁽¹⁾
HEX ADDRESS RANGE
0200 0000
0200 0004
0200 0008
0200 000C
0200 0010
0200 0014−0200 001C
0200 0020
0200 0024
0200 0028
0200 002C
0200 0030
ACRONYM
QOPT
QSRC
QCNT
QDST
QIDX
—
QSOPT
QSSRC
QSCNT
QSDST
QSIDX
(1) All the QDMA and Pseudo registers are write accessible only.
REGISTER NAME
QDMA options parameter
QDMA source address
QDMA frame count
QDMA destination address
QDMA index
Reserved
QDMA pseudo options
QDMA pseudo source address
QDMA pseudo frame count
QDMA pseudo destination address
QDMA pseudo index
Table 4-9. PLL Controller Registers
HEX ADDRESS RANGE
01B7 C000
01B7 C004−01B7 C0FF
01B7 C100
01B7 C104−01B7 C10F
01B7 C110
01B7 C114
01B7 C118
01B7 C11C
01B7 C120
01B7 C124
01B7 C128−01B7 DFFF
ACRONYM
PLLPID
—
PLLCSR
—
PLLM
PLLDIV0
PLLDIV1
PLLDIV2
PLLDIV3
OSCDIV1
—
REGISTER NAME
Peripheral identification
(C6713/13B value: 0x00010801 for PLL Controller)
Reserved
PLL control/status register
Reserved
PLL multiplier control
PLL controller divider 0
PLL controller divider 1
PLL controller divider 2
PLL controller divider 3
Oscillator divider 1
Reserved
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