LP8552_14 Datasheet, PDF (25/49 Pages) Texas Instruments – LP8552 High-Efficiency LED Backlight Driver For Notebooks

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LP8552
SNVS693E – SEPTEMBER 2011 – REVISED SEPTEMBER 2014
<>Data from master [ ] Data from slave
S
Slave Address
(7 bits)
'0' A
Control Register Add.
(8 bits)
A
Register Data
(8 bits)
AP
Data transfered,
R/W
byte + Ack
From Slave to Master
From Master to Slave
A - ACKNOWLEDGE (SDA Low)
S - START CONDITION
P - STOP CONDITION
Register Write Format
Figure 24. Register Write
S
Slave Address
(7 bits)
'0' A
Control Register Add.
(8 bits)
A Sr
Slave Address
(7 bits)
'1' A
Data- Data
(8 bits)
A/
NA
P
R/W
From Slave to Master
From Master to Slave
Data transfered, byte +
R/W Ack/NAck
Direction of the transfer
will change at this point
A - ACKNOWLEDGE (SDA Low)
NA - ACKNOWLEDGE (SDA High)
S - START CONDITION
Sr - REPEATED START CONDITION
P - STOP CONDITION
Register Read Format
Figure 25. Register Read
8.5.2 EEPROM
EEPROM memory stores various parameters for chip control. The 64-bit EEPROM memory is organized as 8 x 8
bits. The EEPROM structure consists of a register front-end and the non-volatile memory (NVM). Register data
can be read and written through the serial interface, and data is effective immediately. To read and program
NVM, separate commands need to be sent. Erase and program voltages are generated on-chip charge pump, no
other voltages than normal input voltage are required. A complete EEPROM memory map is shown in Table 7.
NOTE
EEPROM NVM can be programmed or read by customer for bench validation.
Programming for production devices should be done in TI production test, where
appropriate checks are performed to confirm EEPROM validity. Writing to EEPROM
Control register of production devices (for burning or reading EEPROM) is not
recommended. If special EEPROM configuration is required, please contact the TI Sales
Office for availability.
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