LM4947_14 Datasheet, PDF (25/37 Pages) Texas Instruments – Mono Class D and Stereo Audio Sub-System with OCL Headphone Amplifier and National 3D

LM4947, LM4947TLEVAL
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Application Information
SNAS349C – JUNE 2006 – REVISED NOVEMBER 2007
I²C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ID_ENB: This is the address select input pin.
I²C COMPATIBLE INTERFACE
The LM4947 uses a serial bus which conforms to the I²C protocol to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I²C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4947.
The I²C address for the LM4947 is determined using the ID_ENB pin. The LM4947's two possible I²C chip
addresses are of the form 111110X₁0 (binary), where X₁ = 0, if ID_ADDR is logic LOW; and X₁ = 1, if ID_ENB is
logic HIGH. If the I²C interface is used to address a number of chips in a system, the LM4947's chip address can
be changed to avoid any possible address conflicts.
The bus format for the I²C interface is shown in Figure 3. The bus format diagram is broken up into six major
sections:
The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will
alert all devices attached to the I²C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is HIGH.
After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM4947 has received the address correctly, then it
holds the data line LOW during the clock pulse. If the data line is not held LOW during the acknowledge clock
pulse, then the master should abort the rest of the data transfer to the LM4947.
The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable HIGH.
After the data byte is sent, the master must check for another acknowledge to see if the LM4947 received the
data.
The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH.
The data line should be held HIGH when not in use.
I²C INTERFACE POWER SUPPLY PIN (I²CV_DD)
The LM4947's I²C interface is powered up through the I²CV_DD pin. The LM4947's I²C interface operates at a
voltage level set by the I²CV_DD pin which can be set independent to that of the main power supply pin V_DD. This
is ideal whenever logic levels for the I²C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
Table 3. Chip Address
A7
A6
A5
A4
A3
A2
A1
A0
Chip Address
1
1
1
1
1
0
EC
0
ID_ADDR = 0
1
1
1
1
1
0
0
0
ID_ADDR = 1
1
1
1
1
1
0
1
0
Mode Control
Table 4. Control Registers
D7
D6
D5
D4
D3
D2
0
0
SE/Diff
0
OCL (select)
MC2
(select)
D1
MC1
D0
MC0
Copyright © 2006–2007, Texas Instruments Incorporated
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