ADS8528_14 Datasheet, PDF (25/52 Pages) Texas Instruments – 12-, 14-, 16-Bit, Eight-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS

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ADS8528
ADS8548
ADS8568
SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011
GENERAL DESCRIPTION
The ADS8528/48/68 series includes eight 12-, 14-, and 16-bit analog-to-digital converters (ADCs), respectively,
that operate based on the successive approximation register (SAR) architecture. This architecture is designed on
the charge redistribution principle, which inherently includes a sample-and-hold function. The eight analog inputs
are grouped into four channel pairs. These channel pairs can be sampled and converted simultaneously,
preserving the relative phase information of the signals of each pair. Separate conversion start signals allow
simultaneous sampling on each channel pair of four, six, or eight channels. These devices accept single-ended,
bipolar analog input signals in the selectable ranges of ±4VREF or ±2VREF with an absolute value of up to
±12V; see the Analog Inputs section.
The devices offer an internal 2.5V or 3V reference source followed by a 10-bit digital-to-analog converter (DAC)
that allows the reference voltage VREF to be adjusted in 2.44mV or 2.93mV steps, respectively.
The ADS8528/48/68 also offer a selectable parallel or serial interface that can be used in hardware or software
mode; see the Device Configuration section for details. The Analog and Digital sections describe the functionality
and control of the device in detail.
ANALOG
This section addresses the analog input circuit, the ADCs and control signals, and the reference design of the
device.
Analog Inputs
The inputs and the converters are of single-ended bipolar type. The absolute voltage range can be selected
using the RANGE pin (in hardware mode) or RANGE_x bits (in software mode) in the Configuration (CONFIG)
Register to either ±4VREF or ±2VREF. With the internal reference set to 2.5V (VREF bit C13 = 0 in the CONFIG
Register), the input voltage range can be ±10V or ±5V. With the internal reference source set to 3V (CONFIG bit
C13 = 1), an input voltage range of ±12V or ±6V can be configured. The logic state of the RANGE pin is latched
with the falling edge of BUSY (if CONFIG bit C26 = 0).
The input current on the analog inputs depends on the actual sample rate, input voltage, and signal source
impedance. Essentially, the current into the analog inputs charges the internal capacitor array only during the
sampling period (t_ACQ). The source of the analog input voltage must be able to charge the input capacitance of
10pF in ±4VREF mode or of 20pF in ±2VREF mode to a 12-, 14-, or 16-bit accuracy level within the acquisition
time; see Figure 4. During the conversion period, there is no further input current flow and the input impedance is
greater than 1MΩ. To ensure a defined start condition, the sampling capacitors of the ADS8528/48/68 are
pre-charged to a fixed internal voltage before switching into sampling mode.
To maintain the linearity of the converter, the inputs should always remain within the specified range shown in
the Electrical Characteristics table. The minimum –3dB bandwidth of the driving operational amplifier can be
calculated using Equation 1:
ln(2)(n + 1)
f_3dB =
2pt_ACQ
(1)
where:
n = 12, 14, or 16; n is the resolution of the ADS8528/48/68
With a minimum acquisition time of t_ACQ = 280ns, the required minimum bandwidth of the driving amplifier is
5.2MHz for the ADS8528, 6.0MHz for the ADS8548, or 6.7MHz for the ADS8568. The required bandwidth can be
lower if the application allows a longer acquisition time. A gain error occurs if a given application does not fulfill
the bandwidth requirement shown in Equation 1.
Copyright © 2011, Texas Instruments Incorporated
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