ADS5474_14 Datasheet, PDF (25/41 Pages) Texas Instruments – 14-Bit, 400-MSPS Analog-to-Digital Converter

ADS5474
www.ti.com
SLAS525B – JULY 2007 – REVISED FEBRUARY 2012
For jitter-sensitive applications, the use of a differential clock has some advantages at the system level. The
differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a
differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications
because the board level clock jitter is superior.
Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. In
the case of a sinusoidal clock, larger amplitudes result in higher clock slew rates and reduces the impact of clock
noise on jitter. At high analog input frequencies, the sampling process is sensitive to jitter. And at slow clock
frequencies, a small amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR
degradation. Figure 43 demonstrates a recommended method for converting a single-ended clock source into a
differential clock; it is similar to the configuration found on the evaluation board and was used for much of the
characterization. See also Clocking High Speed Data Converters (SLYT075) for more details.
0.1 mF
Clock
Source
CLK
ADS5474
CLK
Figure 43. Differential Clock
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible, the ADS5474 features good tolerance to
clock common-mode variation (as shown in Figure 44 and Figure 45). Additionally, the internal ADC core uses
both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided.
Performance degradation as a result of duty cycle can be seen in Figure 46.
90
75
85
230 MHz
70 MHz
10 MHz
80
10 MHz
70
351 MHz
70 MHz
75
351 MHz
70
65
65
230 MHz
60
60
55
f_S = 400 MSPS
V_CLK = 3 V_PP
50
0
1
2
3
4
5
Clock Common Mode - V
Figure 44. SFDR versus Clock Common Mode
55
f_S = 400 MSPS
V_CLK = 3 V_PP
50
0
1
2
3
4
5
Clock Common Mode - V
Figure 45. SNR versus Clock Common Mode
Copyright © 2007–2012, Texas Instruments Incorporated
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