DM383_13 Datasheet, PDF (243/267 Pages) Texas Instruments – DM383 DaVinc Digital Media Processor

DM383
www.ti.com
SPRS870B – APRIL 2013 – REVISED DECEMBER 2013
8.14 MultiMedia Card/Secure Digital/Secure Digital Input Output (MMC/SD/SDIO)
The device includes 3 MMC/SD/SDIO Controllers which are compliant with MMC V4.3, Secure Digital Part
1 Physical Layer Specification V2.00 and Secure Digital Input Output (SDIO) V2.00 specifications.
The device MMC/SD/SDIO Controller has the following features:
• MultiMedia card (MMC)
• Secure Digital (SD) memory card
• MMC/SD protocol support
• SDIO protocol support
• Programmable clock frequency
• 1024 byte read/write FIFO to lower system overhead
• Slave EDMA transfer capability
• SD High capacity support
• SDXC card support
– Supports only SDHC clock rates
– Booting from SDXC cards is not supported
8.14.1 MMC/SD/SDIO Peripheral Register Descriptions
The MMC/SD/SDIO peripheral registers are described in the device-specific Technical Reference Manual.
Each register is documented as an offset from a base address for the peripheral. The base addresses for
all of the peripherals are in the device memory map (see Section 2.10).
8.14.2 MMC/SD/SDIO Electrical Data/Timing
Table 8-61. Timing Requirements for MMC/SD/SDIO
(see Figure 8-75, Figure 8-77)
NO
.
1 t_{su(CMDV-CLKH)}
2 t_h(CLKH-CMDV)
3 t_{su(DATV-CLKH)}
4 t_h(CLKH-DATV)
Setup time, SD_CMD valid before SD_CLK rising clock edge
Hold time, SD_CMD valid after SD_CLK rising clock edge
Setup time, SD_DATx valid before SD_CLK rising clock edge
Hold time, SD_DATx valid after SD_CLK rising clock edge
OPP100/OPP120/
Turbo/Nitro
ALL MODES
MIN
MAX
4.1
1.9
4.1
1.9
UNIT
ns
ns
ns
ns
Table 8-62. Switching Characteristics Over Recommended Operating Conditions for MMC/SD/SDIO
(see Figure 8-74 through Figure 8-77)
OPP100/OPP120/
Turbo/Nitro
NO.
PARAMETER
MODES
3.3 V STD
1.8 V SDR12
3.3 V HS
1.8 V SDR25
UNIT
MIN
MAX
MIN
MAX
7 ^fop(CLK)
t_c(CLK)
8 ^fop(CLKID)
t_c(CLKID)
9 t_w(CLKL)
10 t_w(CLKH)
Operating frequency, SD_CLK
Operating period: SD_CLK
Identification mode frequency, SD_CLK
Identification mode period: SD_CLK
Pulse duration, SD_CLK low
Pulse duration, SD_CLK high
41.7
2500.0
0.5*P ⁽¹⁾
0.5*P ⁽¹⁾
24
20.8
400
2500.0
0.5*P ⁽¹⁾
0.5*P ⁽¹⁾
48 MHz
ns
400 kHz
ns
ns
ns
(1) P = SD_CLK period.
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DM383
Peripheral Information and Timings 243