TPS24750 Datasheet, PDF (24/42 Pages) Texas Instruments – 12A eFuse Circuit Protector with Current Monitor

TPS24750
TPS24751
SLVSC87 – OCTOBER 2013
www.ti.com
START-UP OF HOT-SWAP CIRCUIT BY VCC OR EN
The connection and disconnection between a load and the input power bus are controlled by turning on and
turning off the internal FET.
The TPS2475x has two ways to turn on the internal FET :
• Increasing V_VCC above UVLO upper threshold while EN is already higher than its upper threshold sources
current to the gate of internal FET. After an inrush period, the TPS2475x fully turns on internal FET.
• Increasing EN above its upper threshold while V_VCC is already higher than the UVLO upper threshold sources
current to the gate of internal FET. After an inrush period, the TPS2475x fully turns on internal FET.
The EN pin can be used to start up the TPS2475x at a selected input voltage V_VCC.
To isolate the load from the input power bus, the internal FET can be disabled by any of the following conditions:
UVLO, EN, load current above the current-limit threshold, hard short at load, OV, or OTSD. Three separate
mechanisms will disable the internal FET by pulling down the GATE as described below:
1. GATE is pulled down by an 11-mA current source when any of the following occurs.
– The fault timer expires during an overload current fault (V_IMON > 675 mV).
– V_EN is below its falling threshold.
– V_VCC drops below the UVLO threshold.
– V_OV is above its rising threshold.
2. GATE is pulled down by a 1-A current source for 13.5 μs when a hard output short circuit occurs and V_{(VCC –}
SENSE) ^{is greater than 60 mV, that is, the fast-trip shutdown threshold. After fast-trip shutdown is complete, an}
11-mA sustaining current ensures that the internal FET remains off.
3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising
threshold.
FAULT DETECTION OF INTERNAL MOSFET SHORT
One of the salient features of the TPS24752, TPS24753 is the detection of short-circuited internal FET and flag
the output on FLTb pin. The FLTb is pulled low to indicate a FET short if all the following conditions occur.
• EN is below its threshold voltage.
• V_VCC is above the UVLO threshold.
• V_IMON > 103 mV.
The fact that GATE is turned off but current is still flowing through R_SENSE indicates a drain-to-source short.
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