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| TPD3S716-Q1 Datasheet, PDF (24/32 Pages) Texas Instruments – Automotive USB 2.0 Interface Protection with Adjustable Current Limit and Short-to-Battery, Short-Circuit Protection | |||
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TPD3S716-Q1
SLVSDH9C â MARCH 2016 â REVISED JUNE 2016
Layout Example (continued)
www.ti.com
VBUS
D-
D+
GND
USB2.0 Connector
Legend
To Processor
To Processor
N.C.
IADJ
VBUS_CON
VBUS_SYS
VBUS_CON
VBUS_SYS
GND
GND
TPD3S716-Q1
VD-
D-
VD+
D+
VEN
FLT
DEN
VIN
Pin to GND
VIA to 3.3V Plane
VIA to 5V Plane
VIA to GND Plane
Figure 30. Typical Layout Example for TPD3S716-Q1
To Transceiver
To Transceiver
To Transceiver
11.3 Layout Optimized for Thermal Performance
Figure 31 and Figure 32 show images from a real PCB design optimized for the best thermal performance for
TPD3S716-Q1. This PCB layout has 6 layers (2 signal and 4 plane layers). The 2 signal layers are the outer
layers of the PCB and constructed with 2-oz copper, and the 4 internal plane layers are constructed with 1-oz
copper. Using this PCB layout yielded an RθJA(CUSTOM) = 57 (°C/W). The images contain rough dimensions of the
copper traces and pours used around the device. One key strategy to optimize thermal performance of the
device is to maximize the area of the copper pours and traces used to route the device power, GND, and signal
pins when possible. Another key strategy is to maximize the copper weight of the PCB metal layers. This
example demonstrates that excellent thermal performance can be achieved with TPD3S716-Q1 with the proper
PCB layout.
24
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