SRC4192-Q1_16 Datasheet, PDF (24/37 Pages) Texas Instruments – 192-kHz Stereo Asynchronous Sample-Rate Converters

SRC4192-Q1
SLFS081A – OCTOBER 2015 – REVISED NOVEMBER 2015
www.ti.com
LRCKO
BCKO
SDOUT
t_SOH
t_DOPD
t_SOL
t_DOH
Figure 62. Output Port Timing
The bit clock is either input or output at BCKO (pin 25). In Slave mode, BCKO is configured as an input pin, and
can operate at rates from 32 f_S to 128f_S, with a minimum of one clock cycle for each data bit. The exception is
the TDM mode, where the BCKO must operate at N × 64 f_S, where N is equal to the number of SRC4192
devices included on the TDM interface. In master mode, BCKO operates at a fixed rate of 64 f_S for all data
formats except TDM, where BCKO operates at the reference clock (RCKI) frequency. Additional information
regarding TDM mode operation is included in the Application and Implementation section.
The left/right word clock, LRCKO (pin 24), can be configured as an input or output pin. In slave mode, LRCKO is
an input pin, while in master mode it is an output pin. In either case, the clock rate is equal to f_S, the output
sampling frequency. The clock duty cycle is fixed to 50% for I²S, Left-Justified, and Right-Justified formats in
master mode. The LRCKO pulse width is fixed to 32 BCKO cycles for the TDM format in master mode.
Table 2 illustrates data format selection for the output port. For the SRC4192-Q1, the OFMT0 (pin 19), OFMT1
(pin 18), OWL0 (pin 17), and OWL1 (pin 16) inputs are used to set the output port data format and word length.
OFMT1
0
0
1
1
OWL1
0
0
1
1
Table 2. Output Port Data Format Selection
OFMT0
0
1
0
1
OWL0
0
1
0
1
OUTPUT PORT DATA FORMAT
Left-Justified
I²S
TDM
Right-Justified
OUTPUT PORT DATA WORD LENGTH
24 bits
20 bits
18 bits
16 bits
10.3.3 Soft Mute Function
The soft mute function of the SRC4192-Q1 device is invoked by forcing the MUTE input (pin 14) high. The soft
mute function slowly attenuates the output signal level down to all zeroes ±1LSB of dither, which provides an
artifact-free muting of the audio output port.
10.3.4 Ready Output
The SRC4192-Q1 device includes an active low ready output called RDY (pin 15). The RDY pin is an output from
the rate estimator block, which indicates that the input-to-output sampling frequency ratio has been determined.
The ready signal can be used as a flag or indicator output. The ready signal can also be connected to the active
high MUTE input (pin 14) to provide an auto-mute function, so that the output port is muted when the rate
estimator is in transition.
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