SN75DP126 Datasheet, PDF (24/41 Pages) Texas Instruments – DisplayPort™ 1:2 Re-Driver Switch with TMDS Translator

SN75DP126
SLLSEA9A – FEBRUARY 2012 – REVISED MARCH 2012
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Implementing the EN Signal
The SN75DP126 EN input gives control over the device reset and to place the device into Shutdown mode.
When EN is low, all DPCD and local I²C registers are reset to their default values, and all Main Link lanes are
disabled.
It is critical to reset the digital logic of the SN75DP126 after the V_CC supply (and V_DD supply for SN75DP126DS)
is stable (that is, the power supply has reached the minimum recommended operating voltage). To reset the
digital logic, transition the EN input from a low level to a high level. A system may provide a control signal to the
EN signal that transitions low to high after the power supply is (or supplies are) stable, or implement an external
capacitor connected between EN and GND, to allow delaying the EN signal during power up. Both
implementations are shown in the following figures.
V_DD or
V_{DD_DREG}
open drain
GPO
EN
output
C
EN
R_EN = 150 kW
C
controller
SN75DP126
Figure 28. EN Input from Active Controller
SN75DP126
Figure 27. External Capacitor Controlled EN
When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of
the V_CC (and V_DD when applicable) supply, where a slower ramp-up results in a larger value external capacitor.
Refer to the latest reference schematic for the SN75DP126 device and/or consider approximately 200nF
capacitor as a reasonable first estimate for the size of the external capacitor.
When implementing an EN input from an active controller, it is recommended to use an open drain driver if the
EN input is driven. This protects the EN input from damage of an input voltage greater than V_{DD_DREG} (or V_DD).
Hot Plug Detect (HPD) and Cable Adapter Detect (CAD) Description
The SN75DP126 drives the source-side Hot Plug Detect (HPD_SRC) signal output high to indicate to the GPU or
graphics source that at least one sink has been detected and selected for connectivity; when no sink is selected
the HPD_SRC is driven low. A high-level DP_HPD_SNK input indicates a DisplayPort sink device is connected,
and a high-level TMDS_HPD_SNK input indicates a HDMI/DVI sink device is connected.
When DP_HPD_SNK is high, the DisplayPort sink is selected if the TMDS_HPD_SNK input is low. When
TMDS_HPD_SNK is high, the HDMI/DVI sink is selected if the DP_HPD_SNK input is low. If both DP_HPD_SNK
and TMDS_HPD_SNK inputs are high, then the PRIORITY input determines which sink is selected.
When the DisplayPort sink is selected, the CAD_SNK input indicates whether a DP sink (CAD_SNK = low) or a
TMDS sink (CAD_SNK = high) is connected. The level of CAD_SNK is passed to the CAD_SRC output when the
DisplayPort sink is selected. When the HDMI/DVI sink is selected, the CAD_SRC output is driven high regardless
of the value input on CAD_SRC.
A sink is determined to be disconnected when the corresponding HPD_SNK input goes low for a duration of
t_T(HPD). When switching from one sink to the other based on the PRIORITY selection, that is, both sinks are
connected and either PRIORITY has changed or the sink with higher PRIORITY was connected after the sink
with lower PRIORITY, the SN75DP126 asserts HPD_SRC for a duration at least t_T(HPD) before the switchover
connection is established.
Through the local I²C interface it is possible to force the device to ignore DP_HPD_SNK, TMDS_HPD_SNK, and
CAD_SNK, and control HPD_SRC and CAD_SRC directly.
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