LM5064_16 Datasheet, PDF (24/62 Pages) Texas Instruments – Negative Voltage System Power Management and Protection IC

LM5064
SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013
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Option A: The configuration shown in Figure 10 requires three resistors (R1-R3) to set the thresholds.
VCC
R1 _UVLO/EN
2.48V
R2
2.47V
OVLO
R3
VEE
20 PA
LM5064
TIMER AND GATE
LOGIC CONTROL
21 PA
V_SYS
Figure 10. UVLO and OVLO Thresholds Set By R1-R3
The procedure to calculate the resistor values is as follows:
- Choose the upper UVLO threshold (V_UVH), and the lower UVLO threshold (V_UVL).
- Choose the upper OVLO threshold (V_OVH).
- The lower OVLO threshold (V_OVL) cannot be chosen in advance in this case, but is determined after the values
for R1-R3 are determined. If V_OVL must be accurately defined in addition to the other three thresholds, see
Option B below. The resistors are calculated as follows:
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The lower OVLO threshold is calculated from:
(14)
As an example, assume the application requires the following thresholds: V_UVH = 36V, V_UVL = 32V, V_OVH = 60V.
(15)
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Using standard values of R1 = 200 kΩ, R2 = 8.87 kΩ, and R3 = 7.87 kΩ, the lower OVLO threshold calculates to
56V, and the OVLO hysteresis is 4.4V. Note that the OVLO hysteresis is always slightly greater than the UVLO
hysteresis in this configuration. When the R1-R3 resistor values are known, the threshold voltages and
hysteresis are calculated from the following:
(18)
V_UV(HYS) = R1 x 20 µA
(19)
(20)
(21)
V_OV(HYS) = (R1 + R2) x 21 µA
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