BQ76925_15 Datasheet, PDF (24/43 Pages) Texas Instruments – Host-Controlled Analog Front

bq76925
SLUSAM9C – JULY 2011 – REVISED OCTOBER 2015
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Table 17. VREF_CAL
Address
Name
Type
D7
D6
D5
D4
D3
D2
D1
D0
0x10
VREF_CAL
EEPROM
VREF_OFFSET_CORR
VREF_GAIN_CORR
VREF_OFFSET_CORR: Lower 4 bits of offset-correction factor for reference output. The complete offset-
correction factor is obtained by concatenating this value with the the two most significant bits VREF_OC_5 and
VREF_OC_4, which are stored in the VREF_CAL_EXT register. The final value is a 6-bit signed 2’s complement
number in the range –32 to +31 with a value of 1 mV per LSB. See description of usage in Detailed Description.
VREF_GAIN_CORR: Lower 4 bits of gain correction factor for reference output. The complete gain correction
factor is obtained by concatenating this value with the most significant bit VREF_GC_4, which is stored in the
VREF_CAL_EXT register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with
a value of 0.1% per lsb. See description of usage in Detailed Description.
Table 18. VC1_CAL
Address
Name
Type
D7
D6
D5
D4
D3
D2
D1
D0
0x11
VC1_CAL
EEPROM
VC1_OFFSET_CORR
VC1_GAIN_CORR
VC1_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 1 translation. The complete offset
correction factor is obtained by concatenating this value with the most significant bit VC1_OC_4, which is stored
in the VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15
with a value of 1 mV per lsb. See description of usage in Detailed Description.
VC1_GAIN_CORR: Lower 4 bits of gain correction factor for cell 1 translation. The complete gain correction
factor is obtained by concatenating this value with the most significant bit VC1_GC_4, which is stored in the
VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a
value of 0.1% per lsb. See description of usage in Detailed Description.
Table 19. VC2_CAL
Address
Name
Type
D7
D6
D5
D4
D3
D2
D1
D0
0x12
VC2_CAL
EEPROM
VC2_OFFSET_CORR
VC2_GAIN_CORR
VC2_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 2 translation. The complete offset
correction factor is obtained by concatenating this value with the most significant bit VC2_OC_4, which is stored
in the VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15
with a value of 1 mV per LSB. See description of usage in See description of usage in Detailed Description.
VC2_GAIN_CORR: Lower 4 bits of gain correction factor for cell 2 translation. The complete gain correction
factor is obtained by concatenating this value with the most significant bit VC2_GC_4, which is stored in the
VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a
value of 0.1% per LSB. See description of usage in Detailed Description.
Table 20. VC3_CAL
Address
Name
Type
D7
D6
D5
D4
D3
D2
D1
D0
0x13
VC3_CAL
EEPROM
VC3_OFFSET_CORR
VC3_GAIN_CORR
VC3_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 3 translation. The complete offset
correction factor is obtained by concatenating this value with the most significant bit VC3_OC_4, which is stored
in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15
with a value of 1 mV per lsb. See description of usage in Detailed Description.
VC3_GAIN_CORR: Lower 4 bits of gain correction factor for cell 3 translation. The complete gain correction
factor is obtained by concatenating this value with the most significant bit VC3_GC_4, which is stored in the
VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range –16 to +15 with a
value of 0.1% per lsb. See description of usage in Detailed Description.
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