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ADS7950 Datasheet, PDF (24/65 Pages) Texas Instruments – 12/10/8-Bit, 1 MSPS, 16/12/8/4-Channel, Single-Ended, MicroPower, Serial Interface ADCs
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A – JUNE 2008 – REVISED JANUARY 2010
www.ti.com
a
CS
tsu 1
1/t throughput (single frame)
tw 1
SCLK
SDO
SDI
1
2
3
4
5
6
td 1
th 1
td 2
DO- DO- DO- DO- DO-11 DO-10
15
14
13
12 MSB MSB-1
tsu2
DI-15 DI-14 DI-13 DI-12 DI-11 DI-10
14
15 16
DO-2 DO-1 DO-0
LSB+2 LSB+1 LSB
td 3
tq
DI-2 DI-1
DI-0
th 2
Figure 46. Serial Interface Timing Diagram for 12-Bit Devices ( ADS7950/51/52/53)
CCSS\
SCLK
SDO
SDI
a
1/t throughput (single frame)
tsu1
123456
td1
th1
td2
DO- DO-
DO-
DO- DO-11 DO-10
15
14
13
12 MSB MSB-1
tsu2
DI-15 DI-14 DI-13 DI-12 DI-11 DI-10
th2
14 15 16
DO-2
LSB
DO-1 DO-0
-
-
tw1
td3
tq
DI-2 DI-1
DI-0
Figure 47. Serial Interface Timing Diagram for 10-Bit Devices (ADS7954/55/56/57)
CSC\S
SCLK
SDO
SDI
a
1/t throughput (single frame)
tsu1
123456
td1
th1
td2
DO- DO-
DO-
DO- DO-11 DO-10
15
14
13
12 MSB MSB-1
tsu2
DI-15 DI-14 DI-13 DI-12 DI-11 DI-10
th2
12 13 16
DO-4
LSB
DO-3
-
DO-0
-
DI-4 DI-3 DI-0
tw1
td3
tq
Figure 48. Serial Interface Timing Diagram for 8-Bit Devices (ADS7958/59/60/61)
The falling edge of CS clocks out DO-15 (first bit of the four bit channel address), and remaining address bits are
clocked out on every falling edge of SCLK until the third falling edge. The conversion result MSB is clocked out
on the 4th SCLK falling edge and LSB on the 15th/13th/11th falling edge respectively for 12/10/8-bit devices. On
the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 16th falling edge
of SCLK.
The device reads a sixteen bit word on the SDI pin while it outputs the data on the SDO pin. SDI data is latched
on every rising edge of SCLK starting with the 1st clock as shown in Figure 46, Figure 47, and Figure 48.
CS can be asserted (pulled high) only after 16 clocks have elapsed.
24
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ADS7959, ADS7960, ADS7961