ADS7870 Datasheet, PDF(24/45 Page) Burr-Brown (TI) – 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM

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ADS7870 Datasheet, PDF (24/45 Pages) Burr-Brown (TI) – 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM

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ADS7870

SBAS124C â DECEMBER 1999 â REVISED DECEMBER 2005

www.ti.com

Gain/Mux Register

The Gain/Mux register (ADDR = 4) contains the bits that configure the PGA gain (G2 â G0) and the input channel

selection (M3 â M0) as shown in Figure 25. This register is also updated when direct mode is used to start a

conversion so its bit definition is compatible with the instruction byte.

GAIN/MUX REGISTER

ADDR

D7 (MSB)

CNV/BSY

ADDR = 4

BIT SYMBOL

D7 CNV/BSY

D6âD4 G2âG0

NAME

Convert/Busy

PGA Gain Select

D3âD0 M3âM0 Input Channel Select

Bold items are power-up default conditions.

VALUE

000

001

010

011

100

101

110

111

See

Figure 21

FUNCTION

Idle Mode

Busy Mode; write = start conversion

PGA Gain = 1

PGA Gain = 2

PGA Gain = 4

PGA Gain = 5

PGA Gain = 8

PGA Gain = 10

PGA Gain = 16

PGA Gain = 20

Determines input channel selection for the requested conversion, differential or

single-ended configuration.

Figure 25. Gain/Mux Register (ADDR = 4)

Input Channel Selection

Bits M3 through M0 configure the switches that determine the input channel selection. The input channels may

be placed in either differential or single-ended configurations. In the case of differential configuration, the

polarity of the input pins is reversible by the state of the M2 bit. The coding for input channels is given in Figure 21

and examples of different input configurations are shown in Figure 20.

Convert/Busy

If the CNV/BSY bit is set to a 1 during a write operation, a conversion starts on the second falling edge of DCLK

after the active edge of SCLK that latched the data into the Gain/Mux register. The CNV/BSY bit may be read

with a read instruction. The CNV/BSY bit is set to 1 in a read operation if the ADS7870 is performing a conversion

at the time the register is sampled in the read operation.

Gain Select

Bits G2 through G0 control the gain of the programmable gain amplifier. PGA gains of 1, 2, 4, 5, 8, 10, 16, and

20 are available. The coding is shown in Figure 25.

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