ADS5463-SP Datasheet, PDF (24/31 Pages) Texas Instruments – CLASS V, 12-BIT, 500-MSPS ANALOG-TO-DIGITAL CONVERTER

ADS5463-SP
SGLS378F – MARCH 2008 – REVISED DECEMBER 2015
Application Information (continued)
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Square Wave or
Sine Wave
0.01 mF
CLK
ADS5463M
CLK
0.01 mF
S0168-05
Figure 18. Single-Ended Clock
Clock
Source
0.1 mF
CLK
ADS5463M
CLK
S0194-02
Figure 19. Differential Clock
For jitter-sensitive applications, the use of a differential clock has advantages (as with any other ADC) at the
system level. The differential clock allows for common-mode noise rejection at the PCB level. With a differential
clock, the signal-to-noise ratio of the ADC is better for high intermediate frequency applications because the
board clock jitter is superior.
A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum
ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise
on jitter. Figure 19 shows this approach. See Clocking High Speed Data Converters (SLYT075) for more details.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking,
the ADS5463 features good tolerance to clock common-mode variation. Additionally, the internal ADC core uses
both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided.
8.1.3 Digital Outputs
The ADC provides 12 data outputs (D11 to D0, with D11 being the MSB and D0 the LSB), a data-ready signal
(DRY), and an overrange indicator (OVR) that equals a logic high when the output reaches the full-scale limits.
The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the
ADS5463. DRY is source-synchronous to the DATA/OVR bits and operates at the same frequency, creating a
half-rate DDR interface that updates data on both the rising and falling edges of DRY. The ADS5463 digital
outputs are LVDS-compatible. Due to the high data rates, care should be taken not to overload the digital outputs
with too much capacitance, which shortens the data-valid timing window. The values given for timing were
obtained with a measured 14-pF parasitic board capacitance to ground on each LVDS line (or 7-pF differential
parasitic capacitance).
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