ADC12L080_14 Datasheet, PDF (24/28 Pages) Texas Instruments – 12-Bit, 80 MSPS, 450 MHz Bandwidth A/D Converter with Internal Reference

ADC12L080
SNAS200A – OCTOBER 2004 – REVISED OCTOBER 2004
www.ti.com
8.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should
not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above
the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not
uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot
that goes above the power supply or below ground. A resistor of about 50Ω to 100Ω in series with any offending
digital input, close to the signal source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC12L080 with a device that is powered from supplies outside the
range of the ADC12L080 supply. Such practice may lead to conversion inaccuracies and even to device
damage.
Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must
charge for each conversion, the more instantaneous digital current flows through V_DR and DR GND. These large
charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate
bypassing and maintaining separate analog and digital areas on the PC board will reduce this problem.
Additionally, bus capacitance beyond the specified 15 pF/pin will cause t_OD to increase, making it difficult to
properly latch the ADC output data. The result could, again, be an apparent reduction in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541, for example). Dynamic performance can also be
improved by adding series resistors at each digital output, close to the ADC12L080, which reduces the energy
coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors
is 100Ω.
Using an inadequate amplifier to drive the analog input. As explained in Section 2.2, the sampling input is
difficult to drive without degrading dynamic performance.
If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade
performance. A small series resistor at each amplifier output and a capacitor at each of the ADC analog inputs to
ground (as shown in Figure 6 and Figure 7) will improve performance. The LMH6702, LMH6628, LMH6622 and
LMH6655 have been successfully used to drive the analog inputs of the ADC12L080.
Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of
phase with each other. Board layout, including equality of the length of the two traces to the input pins, will affect
the effective phase between these two signals. Remember that an operational amplifier operated in the non-
inverting configuration will exhibit more time delay than will the same device operating in the inverting
configuration.
Operating with the reference pins outside of the specified range. As mentioned in Section 2.1, V_REF should
be in the range specified in the Operating Ratings table. Operating outside of these limits could lead to
performance degradation.
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR and SINAD performance.
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