UCD9222-EP_16 Datasheet, PDF (23/37 Pages) Texas Instruments – DIGITAL PWM SYSTEM CONTROLLER WITH 4-BIT, 6-BIT, OR 8-BIT VID SUPPORT

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UCD9222-EP
SLVSBY1 – OCTOBER 2013
DESIGN PARAMETER
K_DC
F_Z
Q_Z
APPROXIMATE
LOWER BOUND
UPPER BOUND
60
103
3 kHz
Fsw/5
0.1
5.0
UNITS
dB
kHz
n/a
The nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from
zero. Typically Limit 0 and Limit 1 would be configured with negative values between –1 and –32 and Limit 2 and
Limit 3 would be configured with positive values between 1 and 31. However, the gain thresholds do not have to
be symmetrical. For example, the four limit registers could all be set to positive values causing the Gain 0 value
to set the gain for all negative errors and a nonlinear gain profile would be applied to only positive error voltages.
The cascaded 1^st order filter section is used to generate the third zero and third pole.
DPWM Engine
The output of the compensator feeds the high resolution DPWM engine. The DPWM engine produces the pulse
width modulated gate drive output from the device. In operation, the compensator calculates the necessary duty
cycle as a digital number representing a percentage from 0 to 100%. The duty cycle value is multiplied by the
configured period to generate a comparator threshold value. This threshold is compared against the high speed
switching period counter to generate the desired DPWM pulse width. This is shown in Figure 14.
Each DPWM engine can be synchronized to another DPWM engine or to an external sync signal via the SyncIn
and SyncOut pins. Configuration of the synchronization function is done through a MFR_SPECIFIC PMBus
command. See the DPWM Synchronization section for more details.
DPWM Engine (1 of 2)
SysClk
SyncIn
Clk
high res
ramp
reset counter
Switch period
Current balance adj
Compensator output
(Calculated duty cycle)
EADC trigger
threshold
S PWM gate drive output
R
Figure 14. DPWM Engine
EADC trigger
SyncOut
Rail/Power Stage Configuration
Unlike many other products in the UCD92xx family, the UCD9222 does not support assigning power stages to
arbitrary rails, or combining multiple power stages on the same rail. The UCD9222 supports up to two single-
phase rails, and the channel number of each rail’s DPWM output must match that of its EAP/EAN feedback
inputs.
Copyright © 2013, Texas Instruments Incorporated
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