TPS70175-Q1 Datasheet, PDF (23/31 Pages) Texas Instruments – DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS

TPS70175-Q1
www.ti.com
SGLS300B – MARCH 2005 – REVISED SEPTEMBER 2010
Figure 32 shows a typical application where the TPS701xx is powering up a DSP. In this application, by pulling
up the SEQ pin, V_OUT2 (core) is powered up first and then V_OUT1 (I/O).
TPS701xx PWP
6V
V_IN1
V_OUT1
5V
DSP
I/O
0.1 µF
0.1 µF
V_IN2
V_SENSE1
PG1
MR2
RESET
MR2
10 µF _{250 kΩ}
6V
PG1
250 kΩ
RESET
>2 V EN
<0.7 V
EN
SEQ
MR1
V_SENSE2
V_OUT2
MR1
10 µF
2.5 V
Core
EN
SEQ
V_OUT2
(Core)
V_OUT1
(I/O)
PG1
95%
83%
95%
83%
RESET
t1
(see Note A)
30 ms
NOTE A: t1 − Time at which both V_OUT1 and V_OUT2 are greater than the PG1 thresholds and MR1 is logic high.
Figure 32. Application Timing Diagram (SEQ = High)
Input Capacitor
For a typical application, an input bypass capacitor (0.1 mF – 1 mF) is recommended. This capacitor filters any
high frequency noise generated in the line. For fast transient condition where droop at the input of the LDO may
occur due to high inrush current, it is recommended to place a larger capacitor at the input as well. The size of
this capacitor is dependent on the output current and response time of the main power supply, as well as the
distance to the V_I pins of the LDO.
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