TPS70145_16 Datasheet, PDF (23/42 Pages) Texas Instruments – Dual-Output Low Dropout Voltage Regulators with Power-Up Sequencing for Split-Voltage DSP Systems

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TPS70145, TPS70148
TPS70151, TPS70158
TPS70102
SLVS222I – DECEMBER 1999 – REVISED AUGUST 2010
APPLICATION INFORMATION
Sequencing Timing Diagrams
This section provides a number of timing diagrams
showing how this device functions in different
configurations.
Application condition: MR2 is tied to PG1, V_IN1 and
V_IN2 are tied to the same input voltage, the SEQ pin
is tied to logic low and the device is toggled with the
enable (EN) function.
When the device is enabled (EN is pulled low), V_OUT1
turns on first and V_OUT2 remains off until V_OUT1
reaches approximately 83% of its regulated output
voltage. At that time, V_OUT2 is turned on. When V_OUT1
reaches 95% of its regulated output, PG1 turns on
(active high). Since MR2 is connected to PG1 for this
application, it follows PG1. When V_OUT2 reaches 95%
of its regulated voltage, RESET switches to high
voltage level after a 120ms delay (see Figure 40).
TPS701xxPWP
(Fixed Output Option)
V_I
V_IN1
V_OUT1
0.1 µF
V_SENSE1
V_OUT1
10 µF
0.1 µF
V_IN2
PG1
MR2
MR2
RESET ^RESET
250 kΩ
EN ^EN
>2 V
<0.7 V
SEQ
MR1
V_SENSE2
V_OUT2
MR1
V_OUT2
10 µF
EN
SEQ
V_OUT2
V_OUT1
PG1
95%
83%
95%
83%
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
120ms
NOTE A: t1 − Time at which both V_OUT1 and V_OUT2 are greater than the PG1 thresholds and MR1 is logic high.
Figure 40. Timing when SEQ = Low
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