TPS57112-Q1 Datasheet, PDF (23/37 Pages) Texas Instruments – 2.95-V to 6-V Input, 2-A Output, 2-MHz, Synchronous Step-Down Switcher With Integrated FETs ( SWIFT™)

TPS57112-Q1
www.ti.com
SLVSAL8 – DECEMBER 2010
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Co >
1
´
1
8 ´ ¦sw Voripple
Irip ple
Where ΔIout is the change in output current, Fsw is the regulators switching frequency and ΔVout is the
allowable change in the output voltage.
(27)
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Equation 28 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 28 indicates the ESR should be less than 55 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 55 mΩ.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, two 22 mF 10 V X5R ceramic capacitors with 3 mΩ of ESR are used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 29 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 29 yields
333 mA.
Resr < ^Voripple
Iripple
(28)
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Icorms = ^{Vout ´ (Vinmax - Vout)}
12 ´ Vinmax ´ L1 ´ ¦sw
(29)
INPUT CAPACITOR
The TPS57112-Q1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7
mF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any
DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the
TPS57112-Q1. The input ripple current can be calculated using Equation 30.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the
maximum input voltage. For this example, one 10 mF and one 0.1 mF 10 V capacitors in parallel have been
selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using Equation 31. Using the design example values, Ioutmax=2 A, Cin=10 mF, Fsw=1
MHz, yields an input voltage ripple of 50 mV and a rms input ripple current of 0.98 A.
Vout
(Vinmin - Vout)
Icirms = Iout ´
´
Vi nm in
V in mi n
(30)
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DVin = ^{Ioutmax ´ 0.25}
Cin ´ ¦sw
(31)
SLOW START CAPACITOR
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
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