TPS54060A_16 Datasheet, PDF (23/53 Pages) Texas Instruments – Step-Down DC–DC Converter

www.ti.com
Feature Description (continued)
PH
EXT
IL
Figure 43. Plot of Synchronizing in CCM
PH
EXT
IL
TPS54060A
SLVSB57C – MARCH 2012 – REVISED JANUARY 2016
PH
EXT
IL
Figure 44. Plot of Synchronizing in DCM
Figure 45. Plot of Synchronizing in PSM
7.3.16 Power Good (PWRGD Pin)
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal
voltage reference the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pull-up resistor
between the values of 10 and 100kΩ to a voltage source that is 5.5V or less. The PWRGD is in a defined state
once the VIN input voltage is greater than 1.5V but with reduced current sinking capability. The PWRGD will
achieve full current sinking capability as VIN input voltage approaches 3V.
The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin
pulled low.
Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: TPS54060A
Submit Documentation Feedback
23