TLV2556_16 Datasheet, PDF (23/39 Pages) Texas Instruments – 11-Channel Low-Power Serial ADC

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TLV2556
SLAS355B – DECEMBER 2001 – REVISED DECEMBER 2015
Feature Description (continued)
8.3.1.1 Data I/O Cycle
The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods,
depending on the selected output data length. During the I/O cycle, the following two operations take place
simultaneously. An 8-bit data stream consisting of address/command and configuration information is provided to
DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. Data input is
ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length of 8, 12, or
16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising
edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling edge of
CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding
bit is clocked out on the falling edge of each succeeding I/O CLOCK.
8.3.1.2 Sampling Period
During the sampling period, one of the analog inputs is internally connected to the capacitor array of the
converter to store the analog input signal. The converter starts sampling the selected input immediately after the
four address/command bits have been clocked into the input data register. Sampling starts on the fourth falling
edge of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling
edge of I/O CLOCK depending on the data-length selection.
After the 8-bit data stream has been clocked in, DATA IN must be held at a fixed digital level until EOC goes high
or INT goes low (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the
influence of external digital noise.
8.3.1.3 Conversion Cycle
A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external
digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by
an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (~25 ns) to
start the OSC. During the conversion period, the device performs a successive-approximation conversion on the
analog input voltage.
When programmed as EOC, pin 19 goes low at the start of the conversion cycle and goes high when the
conversion is complete and the output data register is latched. After EOC goes low, the analog input can be
changed without affecting the conversion result. Because the delay from the falling edge of the last I/O CLOCK
to the falling edge of EOC is fixed, any time-varying analog input signals can be digitized at a fixed rate without
introducing systematic harmonic distortion or noise due to timing uncertainty.
When programmed as INT, pin 19 goes low when the conversion is complete and the output data register is
latched. The next I/O CLOCK rising edge clears the INT output. The time from the last I/O CLOCK falling edge to
the falling INT edge is equivalent to the EOC delay mentioned above plus the maximum conversion time. INT is
cancelled by (or brought to high) by either the next CS falling edge or the next SCLK rising edge (when CS is
held low all of the time for multiple cycles). When CS is held low continuously (for multiple cycles) MSB output
occurs after the first rising edge of I/O CLOCK after EOC is inactive or the falling edge of INT.
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