OPA4820 Datasheet, PDF (23/35 Pages) Texas Instruments – Quad, Unity-Gain Stable, Low-Noise, Voltage-Feedback Operational Amplifier

OPA4820
www.ti.com
DISTORTION PERFORMANCE
The OPA4820 is capable of delivering an exceptionally low
distortion signal at high frequencies and low gains. The
distortion plots in the Typical Characteristics show the
typical distortion under a wide variety of conditions. Most
of these plots are limited to 100dB dynamic range. The
OPA4820 distortion does not rise above −90dBc until
either the signal level exceeds 0.9V and/or the fundamen-
tal frequency exceeds 500kHz. Distortion in the audio
band is ≤ −100dBc.
Generally, until the fundamental signal reaches very high
frequencies or powers, the 2nd-harmonic will dominate the
distortion with a negligible 3rd-harmonic component.
Focusing then on the 2nd-harmonic, increasing the load
impedance improves distortion directly. Remember that
the total load includes the feedback network—in the
noninverting configuration this is the sum of R_F + R_G,
whereas in the inverting configuration this is just R_F (see
Figure 1). Increasing the output voltage swing increases
harmonic distortion directly. Increasing the signal gain will
also increase the 2nd-harmonic distortion. Again, a 6dB
increase in gain will increase the 2nd- and 3rd-harmonic by
6dB even with a constant output power and frequency.
Finally, the distortion increases as the fundamental
frequency increases because of the roll-off in the loop gain
with frequency. Conversely, the distortion will improve
going to lower frequencies down to the dominant
open-loop pole at approximately 100kHz. Starting from the
−85dBc 2nd-harmonic for 2V_PP into 200Ω, G = +2
distortion at 1MHz (from the Typical Characteristics), the
2nd-harmonic distortion will not show any improvement
below 100kHz and will then be:
−85dB − 20log (1MHz/100kHz) = −105dBc
NOISE PERFORMANCE
The OPA4820 complements its low harmonic distortion
with low input noise terms. Both the input-referred voltage
noise and the two input-referred current noise terms
combine to give a low output noise under a wide variety of
operating conditions. Figure 18 shows the op amp noise
analysis model with all the noise terms included. In this
model, all the noise terms are taken to be noise voltage or
current density terms in either nV/√Hz or pA/√Hz.
The total output spot noise voltage is computed as the
square root of the squared contributing terms to the output
noise voltage. This computation is adding all the contribut-
ing noise powers at the output by superposition, then
taking the square root to get back to a spot noise voltage.
Equation 9 shows the general form for this output noise
voltage using the terms presented in Figure 18.
Ǹƪ ƫ E_O +
E^2NI ) ^ǒI_BNR_S^Ǔ2 ) 4kTR_S NG² ) ^ǒI_BIR_F^Ǔ2 ) 4kTR_FNG
(9)
SBOS317D − SEPTEMBER 2004 − REVISED AUGUST 2008
E_NI
R_S
I_BN
1/4
OPA4820
E_O
E_RS
√ 4kTR_S
4kT
R_G
R_F
√ 4kTR_F
R_G
I_BI
4kT = 1.6E − 20J
at 290_ K
Figure 18. Op Amp Noise Analysis Model
Dividing this expression by the noise gain (NG = 1 +
R_F/R_G) will give the equivalent input referred spot noise
voltage at the noninverting input, as shown in Equation 10.
Ǹ ǒ Ǔ E_N +
2
E^2NI ) ^ǒI_BNR_S^Ǔ2 ) 4kTR_S )
I_BIR_F
NG
)
4kTR_F
NG
(10)
Evaluating these two equations for the OPA4820 circuit
presented in Figure 1 will give a total output spot noise
voltage of 6.44nV/√Hz and an equivalent input spot noise
voltage of 3.22nV/√Hz.
DC OFFSET CONTROL
The OPA4820 can provide excellent DC signal accuracy
because of its high open-loop gain, high common-mode
rejection, high power-supply rejection, and low input offset
voltage and bias current offset errors. To take full
advantage of this low input offset voltage, careful attention
to input bias current cancellation is also required. The
high-speed input stage for the OPA4820 has a moderately
high input bias current (9µA typ into the pins) but with a
very close match between the two input
currents—typically 100nA input offset current. The total
output offset voltage may be considerably reduced by
matching the source impedances looking out of the two
inputs. For example, one way to add bias current
cancellation to the circuit of Figure 1 would be to insert a
175Ω series resistor into the noninverting input from the
50Ω terminating resistor. When the 50Ω source resistor is
DC-coupled, this will increase the source impedance for
the noninverting input bias current to 200Ω. Since this is
now equal to the impedance looking out of the inverting
input (R_F || R_G), the circuit will cancel the gains for the bias
currents to the output leaving only the offset current times
the feedback resistor as a residual DC error term at the
output. Using a 402Ω feedback resistor, this output error
will now be less than ±0.5µA × 402Ω = ±208µV at 25°C.
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