LM3S812 Datasheet, PDF (23/585 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S812 Microcontroller
Table 1. Revision History (continued)
Date
April 2009
Revision Description
5369 ■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 148).
■ Added "GPIO Module DC Characteristics" table (see Table 19-4 on page 543).
■ Additional minor data sheet clarifications and corrections.
January 2009
4644
■ Incorrect bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■ Minor corrections to comparator operating mode tables.
■ Additional minor data sheet clarifications and corrections.
November 2008
4283
■ Revised High-Level Block Diagram.
■ Corrected descriptions for UART1 signals.
■ Additional minor data sheet clarifications and corrections were made.
October 2008
4149
■ Added note on clearing interrupts to the Interrupts chapter:
Note:
It may take several processor cycles after a write to clear an interrupt source in order for
NVIC to see the interrupt source de-assert. This means if the interrupt clear is done as
the last action in an interrupt handler, it is possible for the interrupt handler to complete
while NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This can be avoided by either clearing the interrupt source at the
beginning of the interrupt handler or by performing a read or write after the write to clear
the interrupt source (and flush the write buffer)
■ Step 1 of the Initialization and Configuration procedure in the ADC chapter states the wrong register
to use to enable the ADC clock. Sentence changed to:
1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC0 register.
■ Additional minor data sheet clarifications and corrections were made.
June 2008
2972 Started tracking revision history.
June 18, 2012
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