ADS8863_14 Datasheet, PDF (23/49 Pages) Texas Instruments – 16-Bit, 680-kSPS, Serial Interface, microPower, Miniature, True-Differential Input, SAR Analog-to-Digital Converter

ADS8863
www.ti.com
SBAS571A – MAY 2013 – REVISED DECEMBER 2013
4-Wire CS Mode Without a Busy Indicator
This interface option is useful when one or more ADCs are connected to an SPI-compatible digital host.
Figure 54 shows the connection diagram for single ADC, Figure 56 shows the connection diagram for two ADCs.
DIN CONVST
DOUT
SCLK
CS
CNV
SDI
ADC
CLK
Digital Host
Figure 54. Connection Diagram: Single ADC with 4-Wire CS Mode Without a Busy Indicator
In this interface option, DIN is controlled by the digital host and functions as CS. As shown in Figure 55, with DIN
high, a CONVST rising edge selects CS mode, forces DOUT to 3-state, samples the input signal, and causes the
device to enter a conversion phase. In this interface option, CONVST must be held at a high level from the start
of the conversion until all data bits are read. Conversion is done with the internal clock and continues regardless
of the state of DIN. As a result, DIN (functioning as CS) can be pulled low to select other devices on the board.
However, DIN must be pulled high before the minimum conversion time (t_conv-min) elapses and remains high until
the maximum possible conversion time (t_conv-max) elapses. A high level on DIN at the end of the conversion
ensures the device does not generate a busy indicator.
CONVST
t_conv-min
t_conv-max
1/f_sample
DIN = 1
t_ACQ
DIN
SCLK
œœ
1
2 15
16
DOUT
ADC ^Acquiring
STATE ^{Sample N}
Converting
Sample N
End-of-
Conversion
œœ
D15
D14 D1
D0
œœ
Read Sample N
Acquiring Sample N+1
Figure 55. Interface Timing Diagram: Single ADC with 4-Wire CS Mode Without a Busy Indicator
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