ADS5232_14 Datasheet, PDF (23/32 Pages) Texas Instruments – Dual, 12-Bit, 65MSPS, +3.3V Analog-to-Digital Converter

ADS5232
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POWER-DOWN MODE
The ADS5232 has a power-down pin, STPD (pin 45).
The internal pull-down is in default mode for the
device during normal operation. Forcing the STPD pin
high causes the device to enter into power-down
mode. In power-down mode, the reference and clock
circuitry as well as all the channels are powered
down. Device power consumption drops to less than
90mW. As previously mentioned, the ADS5232 also
enters into a power-down mode if the clock speed
drops below 2MSPS (see the Clock Input section).
When STPD is pulled high, the internal buffers driving
REF_T and REF_B are tri-stated and the outputs are
forced to a voltage roughly equal to half of the
voltage on AV_DD. Speed of recovery from the
power-down mode depends on the value of the
external capacitance on the REF_T and REF_B pins. For
SBAS294A – JUNE 2004 – REVISED MARCH 2006
capacitances on REF_T and REF_B less than 1µF, the
reference voltages settle to within 1% of their
steady-state values in less than 500µs. Either of the
two channels can also be selectively powered-down
through the serial interface when it is enabled.
The ADS5232 also has an internal circuit that
monitors the state of stopped clocks. If ADCLK is
stopped for longer than 250ns, or if it runs at a speed
less than 2MHz, this monitoring circuit generates a
logic signal that puts the device in a partial
power-down state. As a result, the power
consumption of the device is reduced when CLK is
stopped. The recovery from such a partial
power-down takes approximately 100µs. This
constraint is described in Table 2.
Table 2. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage
DESCRIPTION
Recovery from power-down mode (STPD = 1 to STPD = 0).
Recovery from momentary clock stoppage ( < 250ns).
Recovery from extended clock stoppage ( > 250ns).
TYP
500µs
10µs
100µs
REMARKS
Capacitors on REF_T and REF_B less than 1µF.
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