ADC12048 Datasheet, PDF (23/36 Pages) National Semiconductor (TI) – 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter

ADC12048
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SNAS105B – APRIL 2000 – REVISED MARCH 2013
b₈: The SYNC bit. When the SYNC bit is set, the SYNC pin is programmed as an input and the converter is in
synchronous mode. In this mode a rising edge on the SYNC pin causes the ADC to hold the input signal and
begin a conversion. When b₁₅ cleared, the SYNC pin is programmed as an output and the converter is in an
asynchronous mode. In this mode the signal at the SYNC pin indicates the status of the converter. The SYNC
pin is high when a conversion is taking place. The SYNC bit is set at power-up.
b₁₁–b₉: The command field. These bits select the mode of operation of the ADC12048. Power-up value is 000.
b₁₁ b₁ b
Command ⁽¹⁾
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0 0 0 Standby command. This puts the ADC in a low power consumption mode
0 0 1 Ful-Cal command. This will cause the ADC to perform a self-calibrating cycle that will correct linearity and zero errors.
0 1 0 Auto-zero command. This will cause the ADC to perform an auto-zero cycle that corrects offset errors.
0 1 1 Reset command. This puts the ADC in an idle mode.
1 0 0 Start command. This will put the converter in a start mode, preparing it to perform a conversion. If in asynchronous mode (b₈ =
“0”), conversions will immediately begin after the programmed acquisition time has ended. In synchronous mode (b₈ = “1”),
conversions will begin after a rising edge appears on the SYNC pin.
(1) Any other values placed in the command field are meaningless. However, if a code of 101 or 110 is placed in the command field and the
CS, RD and WR go low at the same time, the ADC12048 will enter a test mode. These test modes are only to be used by the
manufacturer of this device. A hardware power-off and power-on reset must be done to get out of these test modes.
b₁₂: This is the Bus Width (BW) bit. When this bit is a '0' the ADC12048 is configured to interface with an 8-bit
data bus; data pins D₇–D₀ are active and pins D₁₂–D₉ are in TRI-STATE. When the BW bit is a '1', the
ADC12048 is configured to interface with a 16-bit data bus and data pins D₁₃–D₀ are all active. The BW bit is a
'0' at power-up.
DATA REGISTER (Read Only)
This is a 13-bit read only register that holds the 12-bit +sign conversion result in two's compliment form. All reads
performed from the ADC12048 will place the contents of this register on the data bus. When reading the data
register in 8-bit mode, the sign bit is extended (b₁₂ through b₈ all contain the sign bit).
MSB
LSB
b₁₂
b₁₁
b₁₀
b₉
b₈
b₇
b₆
b₅
b₄
b₃
b₂
b₁
b₀
sign
Conversion Data
Power on State: 0000Hex
b₁₁–b₀: b₁₁ is the most significant bit and b₀ is the least significant bit of the conversion result.
b₁₂: This bit contains the sign of the conversion result: 0 for positive results and 1 for negative.
Functional Description
The ADC12048 is programmed through a digital interface that supports an 8-bit or 16-bit data bus. The digital
interface consists of a 13-bit data input/output bus (D₁₂–D₀), digital control signals and two internal registers: a
write only 13-bit Configuration register and a read only 13-bit Data register.
The Configuration register programs the functionality of the ADC12048. The 13 bits of the Configuration register
are divided into 7 fields. Each field controls a specific function of the ADC12048: the channel selection of the
MUX, the acquisition time, synchronous or asynchronous conversions, mode of operation and the data bus size.
Features and Operating Modes
SELECTABLE BUS WIDTH
The ADC12048 can be programmed to interface with an 8-bit or 16-bit data bus. The BW bit (b₁₂) in the
Configuration register controls the bus size. The bus width is set to 8 bits (D₇–D₀ are active and D₁₂–D₈ are in
TRI-STATE) if the BW bit is cleared or 13 bits (D₁₂–D₀ are active) if the BW bit is set. At power-up the bus width
defaults to 8 bits and any initial programming of the ADC12048 should take this into consideration.
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