ADC12010 Datasheet, PDF (23/30 Pages) National Semiconductor (TI) – 12-Bit, 10 MSPS, 160 mW A/D Converter with Internal Sample-and-Hold

ADC12010
www.ti.com
SNAS185B – APRIL 2003 – REVISED MARCH 2013
The V_DR pin provides power for the output drivers and may be operated from a supply in the range of 2.35V to
V_D (nominal 5V). This can simplify interfacing to 3V devices and systems. DO NOT operate the V_DR pin at a
voltage higher than V_D.
LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining
separate analog and digital areas of the board, with the ADC12010 between these areas, is required to achieve
specified performance.
The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output
current can exhibit high transients that could add noise to the conversion process. To prevent this from
happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the
ADC12010's other ground pins.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the
clock line as short as possible.
Digital circuits create substantial supply and ground current transients. The logic noise thus generated could
have significant impact upon system noise performance. The best logic family to use in systems with A/D
converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the
74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest
supply current transients during clock or signal edges, like the 74F and the 74AC(T) families. In high speed
circuits, however, it is often necessary to use these higher speed devices. Best performance requires careful
attention to PC board layout and to proper signal integrity techniques.
The effects of the noise generated from the ADC output switching can be minimized through the use of 47Ω to
100Ω resistors in series with each data output line. Locate these resistors as close to the ADC output pins as
possible.
Figure 40. Example of a Suitable Layout
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area
is more important than is total ground plane volume.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in
high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to
keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the
generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause
problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to
degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.
Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the
signal path through all components should form a straight line wherever possible.
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