LM3S328 Datasheet, PDF (225/530 Pages) List of Unclassifed Manufacturers – Microcontroller

7.1 Block Diagram
Figure 7-1. GPIO Module Block Diagram
PA0
U0Rx
UART0
PA1
U0Tx
PA2
SSIClk
PA3
SSIFss
SSI
PA4
SSIRx
PA5
SSITx
PB0
CCP0
Timer0 CCP1
PB1
CCP2 Timer1 CCP3
PB2
I2CSCL
I²C
PB3
I2CSDA
PB4
PB5
PB6
PB7
Stellaris^® LM3S328 Microcontroller
PE0
PE1
PD0
PD1
UART1
U1Rx
U1Tx
PD2
PD3
TCK/SWCLK
PC0
TMS/SWDIO
PC1
TRST JTAG
TDI
PC2
TDO/SWO
PC3
PC4
PC5
PC6
CCP5 Timer2 CCP4
PC7
7.2
Signal Description
GPIO signals have alternate hardware functions. Table 7-3 on page 226 lists the GPIO pins and their
analog and digital alternate functions. The AINx analog signals are not 5-V tolerant and go through
an isolation circuit before reaching their circuitry. These signals are configured by clearing the
corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register. The digital alternate hardware
functions are enabled by setting the appropriate bit in the GPIO Alternate Function Select
(GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control
(GPIOPCTL) register to the numeric enoding shown in the table below. Note that each pin must be
programmed individually; no type of grouping is implied by the columns in the table.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting
RST puts the pins back to their default state.
Table 7-1. GPIO Pins With Non-Zero Reset Values
GPIO Pins
PA[1:0]
PA[5:2]
Default State
UART0
SSI0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
1
1
0
0
1
1
0
0
GPIOPCTL
0x1
0x1
July 14, 2014
225
Texas Instruments-Production Data