TPS61280A_16 Datasheet, PDF (22/54 Pages) Texas Instruments – TPS6128xA Low-, Wide- Voltage Battery Front-End DC/DC Converter Single-Cell Li-Ion, Ni-Rich, Si-Anode Applications

TPS61280A, TPS61281A, TPS61282A
SLVSCG9A – MAY 2014 – REVISED SEPTEMBER 2014
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10.5 Programming
10.5.1 Serial Interface Description (TPS61280A)
I²C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus
Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-
up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices
connect to the I²C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or
a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device
addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A
slave device receives and/or transmits data on the bus under control of the master device.
The TPS6128xA device works as a slave and supports the following data transfer modes, as defined in the I²C-
Bus Specification: standard mode (100 kbps) and fast mode (400 kbps), fast mode plus (1 Mbps) and high-speed
mode (3.4 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be
programmed to new values depending on the instantaneous application requirements. Register contents remain
intact as long as supply voltage remains above 2.1V.
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-
mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as HS-
mode. The TPS6128xA device supports 7-bit addressing; 10-bit addressing and general call address are not
supported. The device 7bit address is defined as ‘111 0101’.
It is recommended that the I2C masters initiates a STOP condition on the I2C bus after the initial power up of
SDA and SCL pull-up voltages to ensure reset of the TPS6128xA I2C engine.
10.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 20. All I²C-compatible devices should
recognize a start condition.
DATA
CLK
S
START Condition
P
STOP Condition
Figure 20. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 21). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 22) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data line
stable;
data valid
Change
of data
allowed
Figure 21. Bit Transfer on the Serial Interface
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