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THS4281_14 Datasheet, PDF (22/38 Pages) Texas Instruments – VERY LOW-POWER, HIGH-SPEED, RAIL-TO-RAIL INPUT AND OUTPUT VOLTAGE-FEEDBACK OPERATIONAL AMPLIFIER
THS4281
SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009
4. Connections to other wideband devices on
the board should be made with short direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Low
parasitic capacitive loads (< 4 pF) may not need
an R(ISO), because the THS4281 is nominally
compensated to operate at unity gain (+1 V/V)
with a 2-pF capacitive load. Higher capacitive
loads without an R(ISO) are allowed as the signal
gain increases. If a long trace is required, and the
6-dB signal loss intrinsic to a doubly terminated
transmission line is acceptable, implement a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline
layout techniques). A matching series resistor into
the trace from the output of the THS4281 is used
as well as a terminating shunt resistor at the input
of the destination device. Remember also that the
terminating impedance is the parallel combination
of the shunt resistor and the input impedance of
the destination device: this total effective
impedance should be set to match the trace
impedance. If the 6-dB attenuation of a
doubly-terminated transmission line is
unacceptable, a long trace can be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case, and
use a series resistor (R(ISO) = 10 Ω to 100 Ω, as
noted above) to isolate the capacitive load. If the
input impedance of the destination device is low,
there is signal attenuation due to the voltage
divider formed by R(ISO) into the terminating
impedance. A 50-Ω environment is normally not
necessary onboard, and in fact a higher
impedance environment improves distortion as
shown in the distortion versus load plots.
5. Socketing a high-speed part like the THS4281
is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create a troublesome parasitic
network which can make it almost impossible to
achieve a smooth, stable frequency response.
Best results are obtained by soldering the
THS4281 onto the board.
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THERMAL ANALYSIS
The THS4281 does not incorporate automatic thermal
shutoff protection, so the designer must take care to
ensure that the design does not violate the absolute
maximum junction temperature of the device. Failure
may result if the absolute maximum junction
temperature of +150° C is exceeded. For long-term
dependability, the junction temperature should not
exceed +125°C.
The thermal characteristics of the device are dictated
by the package and the PCB. Maximum power
dissipation for a given package can be calculated
using the following formula.
P Dmax
+
Tmax–TA
q
JA
where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the
case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
1.8
1.6
8-pin SOIC (D) Package
1.4
8-pin MSOP
1.2
(DGK) Package
1
0.8
0.6
0.4
5-pin SOT23
0.2
(DBV) Package
0
−40 −20 0 20 40 60 80 100
TA − Free-Air Temperature − °C
θJA = 97.5°C/W for 8-Pin SOIC (D)
θJA = 180.8°C/W for 8-Pin MSOP (DGK)
θJA = 255.4°C/W for 5-Pin SOT−23 (DBV)
TJ = 125°C, No Airflow
Figure 76. Maximum Power Dissipation vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to consider not only quiescent power
dissipation, but also dynamic power dissipation. Often
maximum power dissipation is difficult to quantify
because the signal pattern is inconsistent, but an
estimate of the RMS value can provide a reasonable
analysis.
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