TAS5720L_16 Datasheet, PDF (22/52 Pages) Texas Instruments – Digital Input Mono Class-D Audio Amplifier

TAS5720L, TAS5720M
SLOS903B – MAY 2015 – REVISED FEBRUARY 2016
www.ti.com
7.3.2.2 Reading from the I²C Interface
As shown in Figure 41, a data-read transfer begins with the master device transmitting a start condition, followed
by the I² device address and the read/write bit. For the data read transfer, both a write followed by a read are
actually done. Initially, a write is done to transfer the address byte of the internal register to be read. As a result,
the read/write bit becomes a 0. After receiving the TAS5720L/M device address and the read/write bit,
TAS5720L/M device responds with an acknowledge bit. In addition, after sending the internal memory address
byte or bytes, the master device transmits another start condition followed by the TAS5720L/M device address
and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving
the address and the read/write bit, the TAS5720L/M device again responds with an acknowledge bit. Next, the
TAS5720L/M device transmits the data byte from the register being read. After receiving the data byte, the
master device transmits a not-acknowledge followed by a stop condition to complete the data-read transfer.
Start
Condition
Acknowledge
Repeat Start
Condition
Acknowledge
Acknowledge
Not
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A0 ACK
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
I²C Device Address and
Read/Write Bit
Subaddress
I²C Device Address and
Read/Write Bit
Figure 42. Single Byte Read Transfer Timing
Data Byte
Stop
Condition
T0036-03
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TAS5720L/M to the master device as shown Figure 43. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Start
Condition
Acknowledge
Repeat Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6 A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I²C Device Address and
Read/Write Bit
Subaddress
I²C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Last Data Byte
Figure 43. Multi-Byte Read Transfer Timing
Stop
Condition
T0036-04
7.3.3 Serial Audio Interface (SAIF)
The TAS5720L/M device SAIF supports a variety of standard stereo serial audio formats including I²S, left-
justifiedand Right Justified. The device also supports a time division multiplexed (TDM) format that is capable of
transporting up to 8 channels of audio data on a single bus. LRCLK and SDIN are sampled on the rising edge of
BCLK.
For the stereo formats (I²S, left-justified and right-justified), the TAS5720L/M device supports BCLK to LRCLK
ratios of 32, 48 and 64. If the BCLK to LRCLK ratio is 64, MCLK can be tied directly to BCLK. Otherwise MCLK
must be driven externally. The valid MCLK to LRCLK ratios are 64, 128, 256 and 512 as long as the frequency of
MCLK is 25MHz or less.
For TDM operation, the TAS5720L/M device supports 4 or 8 channels for single speed (44.1/48 kHz) and double
speed (88.2/96 kHz) sample rates. Each channel occupies a 32-bit time slot, therefore valid BCLK to LRCLK
ratios are 128 and 256. MCLK can be tied to BCLK for all TDM modes or driven externally. If MCLK is driven
externally, the MCLK to LRCLK ratio should be 64, 128, 256 or 512 and MCLK should be no faster than 25MHz.
The TAS5720L/M device selects the channel for playback based on either the I²C base address offset or based
on a dedicated time slot selection register. See the Adjustable I²C Address section for more information.
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