SN74LVTH18502A-EP Datasheet, PDF (22/42 Pages) Texas Instruments – 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SN74LVTH18502AĆEP, SN74LVTH182502AĆEP
3.3ĆV ABT SCAN TEST DEVICES
WITH 18ĆBIT UNIVERSAL BUS TRANSCEIVERS
SCAS744A − DECEMBER 2003 − REVISED JUNE 2004
simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in
the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an
18-bit binary count-up pattern is generated in the shift-register elements of the selected output-mode BSCs on
each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each
falling edge of TCK. Figures 11 and 12 show the 18-bit linear-feedback shift-register algorithms through which
the signature is generated. An initial seed value should be scanned into the BSR before performing
this operation.
2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O
1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O
MSB
2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O
LSB
=
=
1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O
Figure 11. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)
22
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265