DDC101U Datasheet, PDF (22/29 Pages) Texas Instruments – 20-BIT ANALOG-TO-DIGITAL CONVERTER

When operating in the unipolar input range, CDS functions
with either output data format—straight binary or binary
two’s complement. When operating in the bipolar input
range, CDS functions correctly only with binary two’s
complement output data format.
Oversampling Control
Samples/Integration, M
This control sets the number of samples, M, used by the
DDC101 to oversample the initial and final data points. M
can be set for these values: 1, 2, 4, 8, 16, 32, 64, 128, 256.
Broadband noise in the conversion is reduced roughly in
proportion to the square root of M. Therefore, a conversion
with 128 oversamples will have 1/2 the broadband noise of
a conversion with 32 oversamples. See the previous fre-
quency response discussion.
Multiple Integration Control, L
This control sets the number of integrations per conversion
cycle, L. It is used to reduce the data rate, increase the
magnitude of the input signal range, and/or reduce the noise.
The product of L and M must be 256 or less.
Output Format
Two output formats are available for either the unipolar or
bipolar input ranges:
Binary Two’s Complement (BTC) and Straight Binary.
BIPOLAR INPUT RANGE
For Binary Two’s Complement, output data format, the
output word is a 21-bit Two’s Complement word. The first
bit is the sign bit followed by the Most Significant Bit
(MSB), etc. The output range is +100%FS to –100.8%FS,
where FS is 250pC. For the bipolar input range, the output
code table changes with the use of Correlated Double Sam-
pling (CDS). (There is no difference with or without CDS in
the output code table when using the unipolar input range.)
CODE
0 1111 1111 1111 1111 1111
0 1111 1111 1111 1111 1110
0 1000 0000 0000 0000 0001
0 1000 0000 0000 0000 0000
0 0111 1111 1111 1111 1111
0 0000 0000 0000 0000 0001
0 0000 0000 0000 0000 0000
1 1111 1111 0000 0000 0000
INPUT SIGNAL
+100%FS
+100%FS –1LSB
+1LSB
Zero
–1LSB
–100%FS + 1SLB
–100%FS
–100.8%FS
+250pC
0pC
–250pC
–251.95pC
TABLE XII. BTC Code Table — Bipolar Input Range with-
out CDS.
CODE
0 0111 1111 1111 1111 1111
0 0111 1111 1111 1111 1110
0 0000 0000 0000 0000 0001
0 0000 0000 0000 0000 0000
1 1111 1111 1111 1111 1111
1 1000 0000 0000 0000 0001
1 1000 0000 0000 0000 0000
1 0111 1111 0000 0000 0000
INPUT SIGNAL
+100%FS
+100%FS – 1LSB
+1LSB
Zero
–1LSB
–100%FS + 1LSB
–100%FS
–100.8%FS
+250pC
0pC
–250pC
–251.95pC
UNIPOLAR INPUT RANGE
For Binary Two’s Complement, output data format, the
output word is a 21-bit Two’s Complement word. The first
bit is the sign bit followed by the Most Significant Bit
(MSB), etc. The output range is +100%FS to –0.4%FS,
where FS is 500pC.
CODE
0 1111 1111 1111 1111 1111
0 1111 1111 1111 1111 1110
0 0000 0000 0000 0000 0001
0 0000 0000 0000 0000 0000
1 1111 1111 1111 1111 1111
1 1111 1111 0000 0000 0000
INPUT SIGNAL
+100%FS
+100%FS –1LSB
+1SLB
Zero
–1LSB
–0.4%FS
+500pC
0pC
–1.95pC
TABLE X. BTC Code Table—Unipolar Input Range.
For Straight Binary output data format, the output is a 20-bit
straight binary word. The first bit is the Most Significant Bit
(MSB), etc. The output range is +99.6%FS to –0.4%FS in
which +99.6%FS represents positive full scale and –0.4%FS
represents the minimum input.
TABLE XIII. BTC Code Table — Bipolar Input Range with
CDS.
For Straight Binary output data format with the bipolar input
range, the output is a 20-bit straight binary word. The first
bit is the Most Significant Bit (MSB), etc. The output range
is +100%FS to –100%FS in which +100%FS represents
positive full scale and –100%FS represents the negative full
scale. When using the straight binary output data format in
bipolar input range, do not use CDS. This will cause a
negative overflow to occur.
CODE
1111 1111 1111 1111 1111
1111 1111 1111 1111 1110
1000 0000 0000 0000 0001
1000 0000 0000 0000 0000
0111 1111 1111 1111 1111
0000 0000 0000 0000 0000
INPUT SIGNAL
+100%FS
+100%FS – 1LSB
+1LSB
Zero
–1LSB
–100%FS
+250pC
0pC
–250pC
TABLE XIV. Straight Binary Code Table — Bipolar Input
Range without CDS.
SETUP INPUT CODE
CODE
INPUT SIGNAL
Acquisition Time Control—K - 2 bits
1111 1111 1111 1111 1111
1111 1111 1111 1111 1110
0000 0001 0000 0000 0001
0000 0001 0000 0000 0000
0000 0000 0000 0000 0000
+99.6%FS
+99.6%FS –1LSB
+1LSB
Zero
–0.4%FS
498.05pC
–1.95pC
TABLE XI. Straight Binary Code Table — Unipolar Input
Range.
®
DDC101
CODE
RESULT
00
1 Reset clock period, 0 clock period Acquisition Time,
CDS disabled, no initial data point,
01
1 Reset clock period, 0 clock period Acquisition Time
10⁽¹⁾
1 Reset clock period, 15 clock period Acquisition Time
11
1 Reset clock period, 31 clock period Acquisition Time
NOTE: (1) Recommended for continuous integration mode.
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