ADS7947_14 Datasheet, PDF (22/39 Pages) Texas Instruments – 12/10/8-Bit, 2MSPS, Dual-Channel, Unipolar, Pseudo-Differential, Ultralow-Power SAR Analog-to-Digital Converters

ADS7947
ADS7948
ADS7949
SLAS708 – SEPTEMBER 2010
DEVICE OPERATION
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The ADS7947/8/9 are typically operated with either a 16-clock frame or 32-clock frame for ease of interfacing
with the host processor.
16-CLOCK FRAME
Figure 43 through Figure 45 show the devices operating in 16-clock mode. This mode is the fastest mode for
device operation. In this mode, the devices output data from previous conversions while converting the recently
sampled signal.
As shown in Figure 43, the ADS7947 starts acquisition of the analog input from the 14th rising edge of SCLK.
The device samples the input signal on the CS falling edge. SDO comes out of 3-state and the device outputs
the MSB on the CS falling edge. The device outputs the next lower SDO bits on every SCLK falling edge after it
has first seen the SCLK rising edge. The data correspond to the sample and conversion completed in the
previous frame. During a CS low period, the device converts the recently sampled signal. It uses SCLK for
conversions. The number of clocks needed for a conversion for 12-bit and 8-bit devices are different. For the
ADS7947, conversion is complete on the 14th SCLK rising edge. CS can be high at any time after the 14th
SCLK rising edge. The CS rising edge after the 14th SCLK rising edge and before the 29th SCLK falling edge
keeps the device in the 16-clock data frame. The device output goes to 3-state with CS high.
Sample
N
t_CONV
Sample
N+1
t_ACQ
CS
SCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
SDO
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Data from Sample N-1
Figure 43. ADS7947 Operating in 16-Clock Mode without Power-Down (PDEN = 0)
It is also permissible to stop SCLK after device has seen the 14th SCLK rising edge.
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