ADS5474-SP Datasheet, PDF (22/28 Pages) Texas Instruments – Class V, 14-BIT, 400-MSPS ANALOG-TO-DIGITAL CONVERTER

ADS5474-SP
SLAS574A – SEPTEMBER 2013 – REVISED DECEMBER 2013
Clock
Source
0.1 µF
CLK
ADS5474-SP
CLK
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Figure 36. Differential Clock
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible, the ADS5474 features good tolerance to
clock common-mode variation. Additionally, the internal ADC core uses both edges of the clock for the
conversion process. Ideally, a 50% duty-cycle clock signal should be provided.
The ADS5474 is capable of achieving 69.2 dBFS SNR at 350 MHz of analog input frequency. In order to achieve
the SNR at 350 MHz the clock source rms jitter must be at least 144 fsec in order for the total rms jitter to be 177
fsec. A summary of maximum recommended rms clock jitter as a function of analog input frequency is provided
in Table 2. The equations used to create the table are also presented.
Table 2. Recommended RMS Clock Jitter
INPUT FREQUENCY
(MHz)
30
70
130
230
350
450
750
1000
MEASURED SNR
(dBc)
69.3
69.1
69.1
68.8
68.2
67.4
65.6
63.7
TOTAL JITTER
(fsec rms)
1818
798
429
251
177
151
111
104
MAXIMUM CLOCK
JITTER
(fsec rms)
1816
791
417
229
144
110
42
14
Equation 1 and Equation 2 are used to estimate the required clock source jitter.
SNR (dBc) = -20 ´ LOG10 (2 ´ p ´ f_IN ´ j_TOTAL)
(1)
j_TOTAL = (j_ADC² + j_CLOCK²)^1/2
(2)
where:
j_TOTAL = the rms summation of the clock and ADC aperture jitter;
j_ADC = the ADC internal aperture jitter which is located in the data sheet;
j_CLOCK = the rms jitter of the clock at the clock input pins to the ADC; and
f_IN = the analog input frequency.
Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not
required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see
Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC
Devices, on the Texas Instruments web site. Recommended clock distribution chips (CDCs) are the TI
CDC7005, the CDCM7005-SP and CDCE72010. Depending on the jitter requirements, a band pass filter (BPF)
is sometimes required between the CDC and the ADC. If the insertion loss of the BPF causes the clock
amplitude to be too low for the ADC, or the clock source amplitude is too low to begin with, an inexpensive
amplifier can be placed between the CDC and the BPF.
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