DM505_17 Datasheet, PDF (218/290 Pages) Texas Instruments – SoC for Vision Analytics 15mm Package (ABF) Silicon Revision 2.0

DM505
SPRS976D – NOVEMBER 2016 – REVISED JULY 2017
www.ti.com
Traces near the PCB-edges do not have this infinite ground and therefore may radiate more than the
others. Thus, signals (clocks) or power traces (core power) identified to be critical must not be routed in
the vicinity of PCB edges, or, if not avoidable, must be accompanied by a guard ring on the PCB edge.
SPRS91v_PCB_EMC_02
Figure 7-12. Field Lines of a Signal Above Ground
Signal
Power
Ground
Signal
SPRS91v_PCB_EMC_03
Figure 7-13. Guard Ring Routing
The intention of the guard ring is that HF-energy, that otherwise would have been emitted from the PCB
edge, is reflected back into the board where it partially will be absorbed. For this purpose ground traces on
the borders of all layers (including power layer) must be applied as shown in Figure 7-13.
As these traces must have the same (HF–) potential as the ground plane they must be connected to the
ground plane at least every 10 mm.
7.2.6.3.5 Analog and Digital Ground
For the optimum solution, the AGND and the DGND planes must be connected together at the power
supply source in a same point. This ensures that both planes are at the same potential, while the transfer
of noise from the digital to the analog domain is minimized.
7.3 Core Power Domains
This section provides boundary conditions and theoretical background to be applied as a guide for
optimizing a PCB design. The decoupling capacitor and PDN characteristics tables shown below give
recommended capacitors and PCB parameters to be followed for schematic and PCB designs. Board
designs that meet the static and dynamic PDN characteristics shown in tables below will be aligned to the
expected PDN performance needed to optimize SoC performance.
7.3.1 General Constraints and Theory
• Max PCB static/DC voltage drop (IRd) budget of 1.5% of supply voltage when using PMICs without
remote sensing as measured from PMIC’s power inductor and filter capacitor node to Processor input
including any ground return losses.
• Max PCB static/DC voltage drop (IRd) budget can be relaxed to 7.5% of supply voltage when using
TI recommended PMICs with remote sensing at the load as measured from PMIC’s power inductor
and filter capacitor node to Device’s supply input including any ground return losses.
218 Applications, Implementation, and Layout
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback