UCD9240_17 Datasheet, PDF (21/39 Pages) Texas Instruments – Digital PWM System Controller

UCD9240
www.ti.com................................................................................................................................................... SLUS766C – JULY 2008 – REVISED NOVEMBER 2008
declared and the UCD9240 performs the PMBus configured fault recovery. ADC current measurements are
digitally averaged before they are compared against the FAULT threshold. The output current is measured at a
rate of one output rail per 200 microseconds. The current measurements are then passed through a smoothing
filter to reduce noise on the signal and prevent false errors. The output of the smoothing filter asymptotically
approaches the input value with a time constant that is approximately 3.5 times the sampling interval.
Table 4. Output Current Filter Times Constants
NUMBER OF OUTPUT RAILS
1
2
3
4
OUTPUT CURRENT SAMPLING
INTERVALS (µs)
200
400
600
800
FILTER TIME CONSTANTS (ms)
0.7
1.4
2.1
2.8
For example, with a single rail, the filter has the transfer function characteristics (Figure 11) that shows the signal
magnitude at the output of the averaging filter due to a sine wave input for a range of frequencies. This plot
includes an RC analog low pass network, with a corner frequency of 3 kHz, on the current sense inputs.
This averaged current measurement is used for output current fault detection; see “Overcurrent Detection,”
below.
In response to a PMBus request for a current reading, the device returns an average current value. When the
UCD9240 is configured to drive a multi-phase power converter, the device adds the average current
measurement for each of the power stages tied to a power rail.
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
10
100
1.0k
10k
freq in Hz
100k
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Output Current Balancing
When the UCD9240 is configured to drive multiple power stage circuits from one compensator, current balancing
is implemented by adjusting each gate drive output pulse width to correct for current imbalance between the
connected power stage sections. The UCD9240 balances the current by monitoring the current at the CS analog
input for each power stage and then adding a current balance adjustment value to the DPWM ramp threshold
value for each power stage.
When there is more than one power stage connected to the voltage rail, the device continually determines which
stage has the highest measured current and which stage has the lowest measured current. To balance the
currents while maintaining a constant total current, the adjustment value for the power stage with the lowest
current is increased by the same amount as the adjustment value for the power stage with the highest current is
decreased. A slight modification to this algorithm is made to keep the adjustment values positive in order to
ensure that a positive DPWM duty cycle is commanded under all conditions.
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): UCD9240
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