TPS7A4701-EP Datasheet, PDF (21/27 Pages) Texas Instruments – 36-V, 1-A, 4-uVRMS, RF LDO Voltage Regulator

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TPS7A4701-EP
SLVSDQ3 – FEBRUARY 2017
10.3 Thermal Protection
The TPS7A4701-EP contains a thermal shutdown protection circuit to turn off the output current when excessive
heat is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (T_J) of the main
pass-FET exceeds 170°C (typical). Thermal shutdown hysteresis assures that the LDO again resets (turns on)
when the temperature falls to 150°C (typical). Because the TPS7A4701-EP is capable of supporting high input
voltages, a great deal of power can be expected to be dissipated across the device at low output voltages, which
causes a thermal shutdown. The thermal time-constant of the semiconductor die is fairly short, and thus the
output oscillates on and off at a high rate when thermal shutdown is reached until power dissipation is reduced.
For reliable operation, the junction temperature must be limited to a maximum of 125°C. To estimate the thermal
margin in a given layout, increase the ambient temperature until the thermal protection shutdown is triggered
using worst-case load and highest input voltage conditions. For good reliability, thermal shutdown must be
designed to occur at least 45°C above the maximum expected ambient temperature condition for the application.
This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient
temperature and worst-case load.
The internal protection circuitry of the TPS7A4701-EP is designed to protect against thermal overload conditions.
The circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A4701-EP into
thermal shutdown degrades device reliability.
10.4 Estimating Junction Temperature
JEDEC standards now recommend the use of PSI thermal metrics to estimate the junction temperatures of the
LDO while in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These PSI metrics
are determined to be significantly independent of copper-spreading area. The key thermal metrics (Ψ_JT and Ψ_JB)
are given in the Thermal Information table and are used in accordance with Equation 9.
Y_JT:
T
J
=
T
T
+
Y_JT
´
P
D
Y_JB:
T
J
=
T
B
+
Y_JB
´
P
D
where:
• P_D is the power dissipated as explained in Equation 7,
• T_T is the temperature at the center-top of the device package, and
• T_B is the PCB surface temperature measured 1 mm from the device package and centered on the
package edge.
(9)
Copyright © 2017, Texas Instruments Incorporated
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