TPS546C20A Datasheet, PDF (21/97 Pages) Texas Instruments – 4.5-V to 18-V, 35-A Stackable Synchronous Buck Converters With PMBus

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BP3 or BP6
TPS546C20A
SLUSCK1A – JULY 2016 – REVISED AUGUST 2016
Clock Slave
RT SYNC
Clock Slave
SYNC RT
Master
Slave
Clock Slave
RT SYNC
Clock Slave
SYNC RT
Master
Slave
Figure 29. Phase Interleaving Timing
7.3.9.1.3 SYNC Fault
The converter is allowed to stop switching after detecting the SYNC signal is expected, but not present or has
been lost. The device also reports a live (essentially unlatched) sync_flt bit in the STATUS_MFR_SPECIFIC
(80h) register. The SMBALERT is not triggered if the SYNC_FAULT bit goes high. The default SYNC fault
response is as follows.
• For the case of a clock that is lost after it was previously present, the SYNC-loss detection latency is
approximately 10 µs. During this delay time (between when the clock is lost to when the controller detects it),
the clock slave (loop slave or loop master set as clock slave) continues to operate at a frequency that is
approximately 40% less than the free-running frequency. The frequencies of two devices are most likely not
identical during this 10-µs duration. The clock master continues to operate at the free-running frequency
during the 10-µs duration.
• For the case of a clock signal that is never present, both phases (for 2-phase) or the standalone PWM-loop
master (1-phase) remain off (never switch) while waiting for the external clock to arrive.
After the external clock is restored, seven clock cycles are counted and then the rail performs a new soft-start.
No further user intervention (for example, power-cycle, CNTL toggle, CLEAR_FAULTS, or others) is required for
the rail to start up after clock restoration
NOTE
The SYNC fault response can be disabled by setting the SYNC_FAULT_DIS Bit in the
MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h) register. The SYNC_FAULT_DIS
Bit, when set, disables the sync_flt reporting status, and the devices that lost the SYNC
clock input (loop slave or loop master set clock slave) continue to operate at a frequency
approximately 40% less than the free-running frequency for approximately 10 µs, then
back to the free-running frequency without shutting down. But the frequencies of two
devices are most likely not identical because the clock master continues to operate at its
own free-running frequency.
7.3.10 Current Sharing
For two devices to operate in a 2-phase application, the SYNC, VSHARE, and ISHARE pins of both devices
should be connected respectively, as shown in Figure 30. The loop master device shares the same VSHARE
voltage. Essentially the internal COMP voltage is shared with the loop slave by connecting the VSHARE pin of
each device together. The sensed current in each phase is compared first by connecting the ISHARE pin of each
device, then the error current is added into the internal COMP. The resulting voltage is compared with the PWM
ramp to generate the PWM pulse. This current sharing loop maintains the current balance between devices.
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