TPS54202 Datasheet, PDF (21/26 Pages) Texas Instruments – 4.5-V to 28-V Input, 2-A Output, EMI Friendly Synchronous Step Down Converter

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10 Layout
TPS54202
SLVSD26 – APRIL 2016
10.1 Layout Guidelines
• VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
• The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
• Provide sufficient vias for the input capacitor and output capacitor.
• Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
• Do not allow switching current to flow under the device.
• A separate VOUT path should be connected to the upper feedback resistor.
• Make a Kelvin connection to the GND pin for the feedback path.
• Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
• The trace of the VFB node should be as small as possible to avoid noise coupling.
• The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
VOUT
OUTPUT
INDUCTOR
OUTPUT
CAPACITOR
Additional
Vias to the
GND plane
GND
Vias to the
internal SW
node copper
GND
SW
Vias to the
internal SW
node copper
SW node copper
pour area on internal
or bottom layer
VIN ^VIN
INPUT BYPAS
CAPACITOR
BOOST
CAPACITOR
VBST
EN
VFB
TO ENABLE
CONTROL
FEEDBACK
RESISTORS
Figure 29. Board Layout
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