TNETE2004_09 Datasheet, PDF (21/47 Pages) Texas Instruments – MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

TNETE2004
MDIO-MANAGED QuadPHY
FOUR 10BASE-T PHYSICAL-LAYER INTERFACES
SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997
expansion register
Refer to Table 7 for the bit definition of the expansion register.
NO.
15–5
BIT
NAME
RESERVED
4 PARDETFLT
3 LPNPABLE
2 NPABLE
1 PAGERX
0 LPANABLE
† _{RO = read only}
Table 7. Auto-Negotiation Expansion-Register Bit Functions
FUNCTION
DIRECTION†
Reserved. Read as 0.
RO
Parallel detection fault. PARDETFLT indicates multiple links established. This is not supported
by this PHY; hence, PARDETFLT is always read as the inverse of LINK.
RO
Link-partner next-page able. LPNPABLE indicates that the link partner is next-page capable.
RO
Next-page able. This PHY is capable of exchanging next pages, so NPABLE is hardwired to 1.
RO
Page received. PAGERX is set after three identical and consecutive link code words have been
received from the link partner. PAGERX is cleared when the link-partner ability register is read.
RO
Link-partner auto-negotiation able. LPANABLE is set to 1 when the PHY has received fast link
pulses from the link partner.
RO
auto-negotiation next_page transmit register – AN_NEXTPAGE at 0x07
BYTE 1
BYTE 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NEXTPAGE DATA
Figure 11. Auto-Negotiation Next_Page Transmit Register
When written to, this register sets the next page to be transmitted by way of auto-negotiation. Writing to this
register instructs the auto-negotiation system to transmit a next page.
TNETE2004 identification register, QUADB_ID at 0x10
This register is hardwired to the value 0x0005. Writing to this register has no effect.
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