TLV320AIC1109_14 Datasheet, PDF (21/28 Pages) Texas Instruments – Earphone Mute and Microphone Mute

TLV320AIC1109
PRINCIPLES OF OPERATION
SLAS358 − DECEMBER 2001
DTMF generator operation and interface (continued)
Tones from the DTMF generator block are present at all outputs and are controlled by enabling or disabling the
individual output ports. The values that determine the tone frequency are loaded into the tone registers (high
and low) as two separate values.
The values loaded into the tone registers initiate an iterative table look-up function, placing a 6-bit or 7-bit in 2s
complement value into the the tone registers. There is a 2 dB difference in the resulting output of the two
registers, the high tone register having the greater result.
buzzer logic section
The single-ended output BUZZCON is a PDM signal intended to drive a buzzer through an external driver
transistor. The PDM begins as a selected DTMF tones, generated and passed through the receive D/A channel,
and fed back to the transmit channel analog modulator, where a PDM signal is generated and routed to the
BUZZCON output.
support section
The clock generator and control circuit use the master clock input (MCLK) to generate internal clocks to drive
internal counters, filters, and convertors. Register control data is written into and read back from the PCM codec
registers via the control interface.
I²C−bus protocols
The PCM codec serial interface is designed to be I²C-bus compatible and operates in the slave mode. This
interface consists of the following terminals:
SCL: I²C-bus serial clock — This input synchronizes the control data transfer from and to the codec.
SDA:
I²C-bus serial address/data input/output — This is a bidirectional terminal that transfers register
control addresses and data into and out of the codec. It is an open drain terminal and therefore
requires a pullup resistor to V_CC (typical 10 kΩ for 100 kHz).
TLV320AIC1109 has a fixed device select address of {E2}HEX for write mode and {E3}HEX for read mode.
For normal data transfer, SDA is allowed to change only when SCL is low. Changes when SCL is high are
reserved for indicating the start and stop conditions.
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain
stable whenever the clock line is at high. Changes in the data line while the clock line is at high are interpreted
as a start or stop condition.
CONDITION
STATUS
A
Bus not busy
B
Start data transfer
C
Stop data transfer
D
Data valid
Table 8. I²C-Bus Conditions
DESCRIPTION
Both data and clock lines remain at high
A high-to-low transition of the SDA line while the clock (SCL) is high determines a start condition.
All commands must proceed from a start condition.
A low-to-high transition of the SDA line while the clock (SCL) is high determines a stop condition.
All operations must end with a stop condition.
The state of the data line represents valid data when, after a start condition, the data line is stable
for the duration of the high period of the clock signal.
www.ti.com
21