PCM1738_15 Datasheet, PDF (21/47 Pages) Texas Instruments – Audio-Stereo Digital-to-Analog Converter

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CS
MC
t_(MSS)
t_w(MCH)
t_w(MCL)
PCM1738
SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007
t_w(MHH)
1.4 V
t_(MSH)
1.4 V
MDI
MDO
t_(MCY)
t_(MDS)
t_(MDH)
LSB
t_(MOS)
PARAMETER
MIN
MAX
t_(MCY)
MC clock cycle time
100
t_w(MCL)
MC low-level time
40
t_w(MCH)
MC high-level time
40
t_(MHH)
CS high-level time
80
t_(MSS)
CS falling edge to MC rising edge
15
t_(MSH)
CS hold time⁽¹⁾
15
t_(MDH)
MDI hold time
15
t_(MDS)
MDI setup time
15
t_(MOS)
MC falling edge to MDO stable
30
(1) MC rising edge for LSB to CS rising edge
Figure 38. Control Interface Timing
1.4 V
50% of V_DD
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
T0013-09
MODE CONTROL REGISTERS
User-Programmable Mode Controls
The PCM1738 includes a number of user- programmable functions that are accessed via mode control registers.
The registers are programmed using the serial control interface that was previously discussed in this data sheet.
Table 3 lists the available mode control functions, along with their reset default conditions and associated
register index.
Register Map
The mode control register map is shown in Table 4. Each register includes a W/R bit that indicates whether a
register read (W/R = 1) or write (W/R = 0) operation is performed.
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